CS5501-SD datasheet(48/54 Pages) CIRRUS

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tored to signal when data into the output registers

is complete (DCS returns high). The DACK sig-

nal is not needed in this mode and the lockout

signal to the the S1 inputs of registers U9 and

U10 may be disabled by removing the connection

on the circuit board. A place is provided on the

board for this purpose. A pull-up resistor is pro-

vided on the S1 inputs of the registers if the

connection is opened.

SEC (Synchronous External Clocking) Mode

The SEC mode enables the CS5501/CS5503 to be

directly interfaced to microcontrollers which out-

put a clock signal to synchronously input serial

data to an input port. The CS5501/CS5503 will

output its serial data at the rate determined by the

clock from the microcontroller.

Connector P10 allows a microcontroller access to

the CS5501/CS5503 signal lines which are neces-

sary to operate in the SEC mode.

The CSB (chip select bar CS) signal allows the

microcontroller

control

when

the

CS5501/CS5503 is to output data. The DRB (data

ready bar) signal on P10 indicates to the micro-

controller when data from the CS5501/CS5503 is

available. Clock from the microcontroller is input

into SCI (serial clock input) and data output from

the CS5501/CS5503 is presented to the SD (serial

data) pin of the P10 connector. Note that the

jumpers on connectors P9 and P11 must be in the

NC (no connection) position to allow the micro-

controller full control over the signals on P10.

AC (Asynchronous Communication) Mode

(for CS5501 evaluation only)

The AC mode enables the CS5501 to output data

in a UART-compatible format. Data is output as

two characters consisting of one start bit, eight

data bits, and two stop bits each.

The output data rate can be set by a clock input to

the SCI input at connector P10 (see Figure 2).

The jumper on P11 must be in the NC position.

Alternatively an output data bit rate can be se-

lected as a sub-multiple of the external CLKIN

signal to the board or as a sub-multiple of the on-

board 4.9152 MHz oscillator. Counter IC U2

divides its input by 2n where n = 8, 9, ...12. One

of these outputs can be jumper selected at con-

nector P3 (see Figure 1). For example, if the

4.9152 MHz oscillator is selected as the input to

IC U2 then a 1200 baud rate clock can be se-

lected with the jumper at n = 12. Table 3

indicates the baud rates available at connector P3

when the 4.9152 MHz oscillator is used. If the

on-board baud clock is to be used, the jumper on

connector P11 should be in the BC (Baud Clock)

position.

Data Output Interface: RS-232 (for CS5501

evaluation only).

The RS232 port is depicted in Figure 4. Sub-D

connector P6 along with interface IC U11 pro-

vides the necessary circuitry to connect the

CS5501 to an RS-232 input of a computer. For

proper operation the AC (Asynchronous Commu-

nication) data output mode must be selected. In

P-3

Baud Rate CLK Divider

19.2 kHz

99.6 kHz

4.8 kHz

2.4 kHz

1.2 kHz

Table 3. On-Board Baud Rate Generator

Baud Rate Clock Divider (CLK/2

n) with INT CLK on P1 selected.

CLK = 4.9152 MHz

P-11

SCLK Input to CS5501/CS5503

No Connection

Baud Clock

On-Board Baud Rate Clock Input to CS5501/CS5503 SCLK Input.

CDB5501/CDB5503

DS31DB3

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