CS5501-SD datasheet(42/54 Pages) CIRRUS

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INTRODUCTION

The CDB5501/CDB5503 evaluation board pro-

vides maximum flexibility for controlling and

interfacing to the CS5501/CS5503 A/D convert-

ers. The CS5501 or the CS5503 require a minimal

amount of external circuitry. The devices can op-

erate with a crystal (or ceramic resonator) and a

voltage reference.

The evaluation board includes several clock

source options, a 2.5 volt trimmable reference,

and circuitry to support several data interface

schemes. The board operates from +5 and -5 volt

power supplies.

Evaluation Board Overview

The CDB5501/CDB5503 evaluation board in-

cludes extensive support circuitry to aid

evaluation of the CS5501/CS5503. The support

circuitry includes the following sections:

1) A clock generator which has an on-board

oscillator and counter divider IC.

2) A 2.5 volt trimmable voltage reference.

3) A Decimation Counter.

4) A parallel output port (for CS5501 only).

5) An RS-232 interface (for CS5501 only).

6) A micro port (for CS5501 or CS5503).

7) DIP switch and CAL pushbutton.

Clock Generator

The CS5501/CS5503 can operate off its on-chip

oscillator or an off-chip clock source. The evalu-

ation board includes a 4.9152 MHz gate oscillator

and counter-divider chain as the primary clock

source for the CS5501/CS5503. The counter-di-

vider outputs offer several jumper-selectable

frequen cies

clo ck

inp uts

the

CS5501/CS5503. The 4.9152 MHz crystal fre-

quency was chosen to allow the counter-divider

chain to also provide the common serial data rates

(1200, 2400, 4800, etc.) when the CDB5501

evaluation board is configured to provide RS-232

data output. If a different operating frequency for

the CS5501/CS5503 is desired, three options ex-

ist. First, a BNC input is provided to allow an

external CMOS (+5V) compatible clock to be

used. Second, the crystal (Y1) in the on-board

gate oscillator can be changed. Or, third, the on-

chip oscillator of the CS5501/CS5503 can be

used with a crystal connected in the Y2 position.

2. 5 Volt Reference

A 2.5 volt (LT1019CN8-2.5) reference is pro-

vided on the board. Potentiometer R9 allows the

initial value of the reference to be accurately

trimmed.

Decimation Counter

The CS5501/CS5503 updates its internal output

cles of the master clock. Each time the output

though output data is updated at a high rate it

may be desirable in certain applications to acti-

vate the CS to read the data at a much lower rate.

A decimation counter is provided on the board for

this purpose.

The counter reduces the rate at

which the CS line of the CS5501 is activated by

only allowing CS to occur at a sub-multiple of the

DRDY rate.

Parallel Output Port (for CS5501 only)

The output data from the CS5501/CS5503 is in

serial form. Some applications may require the

data to be read in parallel format. Therefore the

evaluation board includes two 8-bit shift registers

with three-state outputs. Data from the CS5501 is

shifted into the registers and then read out in

16 bit parallel fashion. The parallel port comes set

up for 16-bit parallel output but can be reconfig-

ured to provide two 8-bit reads. The parallel port

supports the CS5501 only, since the CS5503 out-

puts 20-bit words.

CDB5501/CDB5503

DS31DB3

CS5501-SD 数据表(PDF) 42 Page - Cirrus Logic

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