CS5501-SD datasheet(52/54 Pages) CIRRUS

52 / 54 page

Oscilloscope Monitoring of SDATA

The output data from either the CS5501 or the

CS5503 can be observed on a dual trace oscillo-

scope with the following hook-up. Set the

evaluation board to operate in the SSC mode.

Connect scope probes to TP9 (SCLK) and TP10

(SDATA). Use a third probe connected to TP8

(DRDY) to provide the external trigger input to

the scope (use falling edge of DRDY to trigger).

With proper horizontal sweep, the SDATA output

bits from the A/D converter can be observed.

Note that if the input voltage to the CS5501 is

adjusted to a mid-code value, the converter will

remain stable on the same output code. This illus-

trates the low noise level of the CS5501. The

CS5503 will exhibit a few LSB’s of noise in its

observed output in agreement with its noise speci-

fications.

Evaluation Board Component Layout and

Design Considerations

Figure 7 is a reproduction of the silkscreen com-

ponent placement of the PC board.

The evaluation board includes design features to

insure proper performance from the A/D con-

verter chip. Separate analog and digital ground

planes have been used on the board to insure

good noise immunity to digital system noise.

Decoupling networks (R6, C7, and R7, C9 in Fig-

ure 6) have been used to eliminate the possibility

of noise on the power supplies on the digital sec-

tion from affecting the analog part of the A/D

converter chip.

The RC network (R10, C16 and C19) on the

output of the LT1019-2.5 reference may not be

needed in all applications. It has been included to

insure the best noise performance from the refer-

ence .

CDB5501/CDB5503

DS31DB3

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