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CS5501-SD 数据表(PDF) 26 Page - Cirrus Logic |
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CS5501-SD 数据表(HTML) 26 Page - Cirrus Logic |
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26 / 54 page ![]() age reference, and the analog signal conditioning circuitry from the same primary source. If sepa- rate supplies are used, it is recommended that the CS5501/CS5503 be powered up first. If a com- mon power source is used for the analog signal conditioning circuitry as well as the A/D con- verter, this power source should be applied before application of power to the digital logic supply. The CS5501/CS5503 exhibit good power supply rejection for frequencies within the passband (dc to 10 Hz). Any small offset or gain error caused by long term drift of the power supplies can be removed by recalibration. Above 10 Hz the digi- tal filter will provide additional rejection. When the benefits of the digital filter are added to the regular power supply rejection the effects of line frequency variations (60 Hz) on the power sup- plies will be reduced greater than 120 dB. If the supply voltages for the CS5501/CS5503 are gen- erated with a dc-dc converter the operating frequency of the dc-dc converter should not oper- ate at the sampling frequency of the CS5501/CS5503 or at integer multiples thereof. At these frequencies the digital filter will not aid in power supply rejection. See Anti-Alias Consid- erations section of this data sheet. CS5501 CS5503 +5V Analog Supply 2 3 0.1 µF CLKIN CLKOUT VD+ 15 10 Ω VA+ 14 11 1 MODE 19 SCLK Optional Clock Source Sleep Mode Control Output Mode Select Serial Data Interface 20 SDATA 16 18 Control Logic CAL SC1 SC2 13 4 17 12 BP/UP AIN 9 Calibration Control Bipolar/ Unipolar Input Select VREF AGND 8 10 5 DGND VD- 6 VA- 7 0.1 µF Analog Signal Source 0.1 µF -5V Analog Supply SLEEP DRDY CS 0 VREF or ±VREF 0.0047 µF NPO * Recommended to reduce high frequency noise +5V Analog Supply Voltage Reference 200 Ω∗ Unused Logic Inputs must be connected to DGND or VD+ +2.5V 10 Ω 0.1 µF Figure 15. Typical Connection Diagram CS5501/CS5503 26 DS31F2 |
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