CS5501-SD datasheet(35/54 Pages) CIRRUS

35 / 54 page

In such asynchronous configurations the CS5501

is operated much like a successive-approximation

converter with a Convert signal and a subsequent

read cycle.

If it is required to latch the 16-bit data, then 2

74HC595 8-bit "shift register with latch" parts

may be used instead of 74HC299’s.

Serial Interfaces

Figures A3 to A8 offer both the hardware and

software interfaces to several industry-standard

microcontrollers using the CS5501’s SEC and

AC output modes. In each instance a system in-

itialization routine is provided which configures

the controller’s I/O ports to accept the CS5501’s

serial data and clock outputs and/or generate its

own serial clock. The routine also sets the

CS5501 into a known state.

For each interface, a second subroutine is also

provided which will collect one complete 16-bit

output word from the CS5501. Figure A5 illus-

trates the detailed timing throughout the

subroutine for one particular interface - the

COPS family interface of Figure A4.

Figure A2. 8-Bit Parallel Interface

+5V

OE2 OE1

OE2

OE1

D10

D11

D12

D13

D14

D15

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

MODE

SDATA

SCLK

DRDY

+5V

SET

RESET

INT

Only needed for

interrupt driven systems

DRDY

(For polling)

CS5501

CS5503

CS5501/CS5503

DS31F2

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