CS5501-SD datasheet(27/54 Pages) CIRRUS

27 / 54 page

The recommended system connection diagram for

the CS5501/CS5503 is illustrated in Figure 15.

Note that any digital logic inputs which are to be

unused should be tied to either DGND or the

VD+ as appropriate. They should not be left float-

ing; nor should they be tied to some other logic

supply voltage in the system.

Power-Up and Initialization

Upon power-up, a calibration cycle must be initi-

ated at the CAL pin to insure a consistent starting

condition and to initially calibrate the device. The

CAL pin must be strobed high for a minimum of

4 clock cycles.

The falling edge will initiate a

calibration cycle. A simple power-on reset circuit

can be built using a resistor and capacitor (see

Figure 16). The resistor and capacitor values

should allow for clock or oscillator startup time,

and the voltage reference stabilization time.

Due to the devices’ low power dissipation and

low temperature drift, no warm-up time is re-

quired to accommodate any self-heating effects.

Sleep Mode

The CS5501/CS5503 include a sleep mode

(SLEEP = DGND) which shuts down the internal

analog and digital circuitry reducing power con-

sumption to less than 10

µW. All calibration

coefficients are retained in memory such that no

time is required after "awakening" for recalibra-

tion. Still, the CS5501/CS5503 will require time

for the digital filter to settle before an accurate

reading will occur after a rising edge on SLEEP

occurs.

Battery Backed-Up Calibrations

The CS5501/CS5503 use SRAM to store calibra-

tion information. The contents of the SRAM will

be lost whenever power is removed from the chip.

Figure 17 shows a battery back-up scheme that

can be used to retain the calibration memory dur-

ing system down time and/or protect it against

intermittent power loss.

Note that upon loss of

power, the SLEEP input goes low, reducing

power consumption to just 10

µW. Lithium cells

of 3.6 V are available which average 1750 mA-

hours before they drop below the typical 2 V

memory-reten tion

specification

the

CS5501/CS5503.

When SLEEP is active (SLEEP = DGND), both

VD+ and VA+ must remain powered to no less

than 2 V to retain calibration memory. The VD-

and VA- voltages can be reduced to 0 V but must

not be allowed to go above ground potential. The

negative supply must exhibit low source imped-

ance in the powered-down state as the current into

the VA+ pin flows out the VA- pin. (AGND is

only a reference node. No power supply current

flows in or out of AGND.) Care should be taken

CS5501

+5V

CAL

SC2

SC1

Figure 16. Power-On Reset Circuitry

(Self-Calibration Only)

CS5501

VD+

Ω

VA+

0.1

µF

+5V

1N4148

AGND

SLEEP

0.1

µF

1N4148

DGND

VD-

VA-

Ω

0.1

µF

-5V

0.1

µF

47k

Ω

CS5503

(2V+Vd) < Vb < 4.5V

Figure 17. Example Calibration Memory Battery

Back-Up Circuit

CS5501/CS5503

DS31F2

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