CS5501-SD datasheet(19/54 Pages) CIRRUS

19 / 54 page

sequence (system offset and system gain) has

been properly performed, additional offset calibra-

tions can be performed by themselves to

reposition the gain slope (the slope factor is not

changed) to adjust its zero reference point to the

new system zero reference value.

A second system calibration mode is available

which uses an input voltage for the zero scale

calibration point, but uses the VREF voltage as

the full scale calibration point.

Whenever a system calibration mode is used,

there are limits to the amount of offset and to the

amount of span which can be accommodated.

The range of input span which can be accommo-

dated in either unipolar or bipolar mode is

restricted to not less than 80% of the voltage on

VREF and not more than 200% of (VREF +

0.1) V. The amount of offset which can be cali-

brated depends upon whether unipolar or bipolar

mode is being used. In unipolar mode the system

calibration modes can handle offsets as positive as

20% of VREF (this is restricted by the minimum

span requirement of 80% VREF) or as negative as

-(VREF + 0.1) V. This capability enables the

unipolar mode of the CS5501/CS5503 to be cali-

brated to mimic bipolar mode operation.

In the bipolar mode the system offset calibration

range is restricted to a maximum of

±40% of

VREF. It should be noted that the span restrictions

limit the amount of offset which can be calibrated.

The span range of the converter in bipolar mode

extends an equidistance (+ and -) from the voltage

used for the zero scale point. When the zero scale

point is calibrated it must not cause either of the

two endpoints of the bipolar transfer function to

exceed the positive or the negative input over-

range points (+(VREF + 0.1) V or - (VREF +

0.1) V). If the span range is set to a minimum

(80% VREF) the offset voltage can move

±40%

VREF without causing the end points of the trans-

fer function to exceed the overrange points.

Alternatively, if the span range is set to 200% of

VREF, the input offset cannot move more than

+0.1 or

0.1 V before an endpoint of the transfer

function exceeds the input overrange limit.

Initiating Calibration

Table 2 illustrates the calibration modes available

in the CS5501/CS5503. Not shown in the table is

the function of the BP/UP pin which determines

whether the converter is calibrated to measure bi-

polar or unipolar signals.

A calibration step is

initiated by bringing the CAL pin (13) high for at

least 4 CLKIN cycles to reset the part and then

bringing CAL low. The states of SC1 (pin 4) and

SC2 (pin 17) along with the BP/UP (pin 12) will

determine the type of calibration to be performed.

The SC1 and SC2 inputs are latched when CAL

goes low. The BP/UP input is not latched and

therefore must remain in a fixed state throughout

the calibration and measurement cycles. Any time

the state of the BP/UP pin is changed, a new cali-

bration cycle must be performed to enable the

CS5501/CS5503 to properly function in the new

mode.

When a calibration step is initiated, the DRDY

signal will go high and remain high until the step

is finished.

Table 2 illustrates the number of

clock cycles each calibration requires.

Once a

calibration step is initiated it must finish before a

new calibration step can be executed. In the two

step system calibration mode, the offset calibra-

tion step must be initiated before initiating the

gain calibration step.

When a self-cal is completed DRDY falls and the

output port is updated with a data word that repre-

sents the analog input signal at the AIN pin.

When a system calibration step is completed,

DRDY will fall and the output port will be up-

dated with the appropriate data value (zero scale

point, or full scale point). In the system calibra-

tion mode, the digital filter must settle before the

output code will represent the value of the analog

input signal.

CS5501/CS5503

DS31F2

CS5501-SD 数据表(PDF) 19 Page - Cirrus Logic

CS5501-SD 数据表(HTML) 19 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

数据表下载