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CS5501-SD 数据表(PDF) 41 Page - Cirrus Logic |
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CS5501-SD 数据表(HTML) 41 Page - Cirrus Logic |
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41 / 54 page ![]() 41 Copyright © Cirrus Logic, Inc. 1998 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CDB5501 CDB5503 CS5501/CS5503 Evaluation Board Features l Operation with on-board clock generator, on- board crystal, or an off-board clock source. l DIP switch selectable or micro port controllable: - Unipolar/Bipolar input range - Sleep Mode-All Cal Modes l On-board Decimation Counter l Multiple Data Output Interface Options: - RS-232 (CS5501) - Parallel Port (CS5501) - Micro Port (CS5501 & CS5503) Description The CDB5501/CDB5503 is an evaluation board de- signed for maximum flexibility when evaluating the CS5501/CS5503 A/D converters. The board can easily be configured to evaluate all the features of the CS5501/CS5503, including changes in master clock rate, calibration modes, output decimation rates, and in- terface modes. The evaluation board interfaces with most microcontrol- lers and allows full control of the features of the CS5501 or CS5503. DIP switch selectable control is also avail- able in the event a microcontroller is not used. The evaluation board also offers computer data interfaces in- cluding RS-232 and parallel port outputs for evaluating the CS5501. All calibration modes are selectable including Self-Cal, System Offset Cal, and System Offset and System Gain Cal. A calibration can be initiated at any time by pressing the CAL pushbutton switch. ORDERING INFORMATION CDB5501 Evaluation Board CDB5503 Evaluation Board I CLKIN AIN Divider OSC VREF Decimation Counter Parallel Port Micro Port RS-232 Port GND -5 +5 CS5501/ CS5503 MAR ‘95 DS31DB3 |
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