CS5501-SD datasheet(22/54 Pages) CIRRUS

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equation which defines settling time, an equation

for the maximum acceptable source resistance is

derived

Rsmax

−64

CLKIN

(20pF+CEXT ) ln 







Ve +

20pF

(100mv)

( 20pF+CEXT )









This equation assumes that the offset voltage of

the buffer is 100 mV, which is the worst case.

The value of Ve is the maximum error voltage

which is acceptable.

For a maximum error voltage (Ve) of 10

µV in

the CS5501 (1/4LSB at 16-bits) and 600 nV in

the CS5503 (1/4LSB at 20-bits), the above equa-

tion indicates that when operating from a

4.096 MHz CLKIN, source resistances up to

84 k

Ω in the CS5501 or 64 kΩ in the CS5503 are

acceptable in the absence of external capacitance

(CEXT = 0). If higher input source resistances

are desired the master clock rate can be reduced

to yield a longer settling time for the 64 cycle pe-

riod.

Analog Input Drift Considerations

The CS5501/CS5503 analog input uses chopper-

stabilization techniques to minimize input offset

drift. Charge injection in the analog switches and

leakage currents at the sampling node are the pri-

mary sources of offset voltage drift in the

converter. Figure 12 indicates the typical offset

drift due to temperature changes experienced after

calibration at 25

°C. Drift is relatively flat up to

about 75

°C. Above 75 °C leakage current be-

comes the dominant source of offset drift.

Leakage currents approximately double with each

°C of temperature increase. Therefore the off-

set drift due to leakage current increases as the

temperature increases. The value of the voltage on

the sample capacitor is updated at a rate deter-

mined by the master clock, therefore the amount

of offset drift which occurs will be proportional to

the elapsed time between samples. In conclusion,

the offset drift increases with temperature and is

inversely proportional to the CLKIN rate.

minimize offset drift with increased temperature,

higher CLKIN rates are desirable. At temperatures

above 100

°C, a CLKIN rate above 1 MHz is rec-

ommended. The effects of offset drift due to

temperature changes can be eliminated by recali-

brating the CS5501/CS5503 whenever the

temperature has changed.

Gain drift within the converter depends predomi-

nately upon the temperature tracking of internal

capacitors. Gain drift is not affected by leakage

currents, therefore gain drift is significantly less

than comparable offset errors due to temperature

increases. The typical gain drift over the specified

temperature range is less than 2.5 LSBs for the

CS5501 and less than 40 LSBs for the CS5503 .

Measurement errors due to offset drift or gain

drift can be eliminated at any time by recalibrat-

ing the converter.

Using the system calibration

mode can also minimize offset and gain errors in

the sig nal cond ition ing circu itry.

The

CS5501/CS5503 can be recalibrated at any tem-

perature to remove the effects of these errors.

Linearity and differential non linearity are not sig-

nificantly affected by temperature changes.

Temperature in Deg. C.

-20

-15

-10

-5

-55

-35

-15

105

125

-320

-240

-160

-80

160

Figure 12. Typical Self-Cal Bipolar Offset vs. Tem-

perature After Calibration at 25

°C

CS5501/CS5503

DS31F2

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