CS5501-SD datasheet(18/54 Pages) CIRRUS

18 / 54 page

represents the gain slope for the input to output

transfer function of the converter. In unipolar

mode the calibration microcontroller determines

the slope factor by dividing the span between the

zero point and the full scale point by the total

resolution of the converter (2

16 for the CS5501,

resulting in 65,536 segments or 2

20 for the

CS5503, resulting in 1,048,578 segments). In bi-

polar mode the calibration microcontroller divides

the span between the zero point and the full scale

point into 524,288 segments for the CS5503 and

32,768 segments for the CS5501. It then extends

the measurement range 524,288 segments for the

CS5503, 32,768 segments for the CS5501, below

the zero scale point to achieve bipolar measure-

ment capability. In either unipolar or bipolar

modes the calculated slope factor is saved and

later used to calculate the binary output code

when an analog signal is present at the AIN pin

during measurement conversions.

System calibration allows the A/D converter to

compensate for system gain and offset errors (see

Figure 9). System calibration performs the same

slope factor calculations as self cal but uses volt-

age values presented by the system to the AIN pin

for the zero scale point and for the full scale

point.

Table 2 depicts the calibration modes

available.

Two system calibration modes are

listed. The first mode offers system level calibra-

tion for system offset and for system gain. This is

a two step calibration. The zero scale point (sys-

tem offset) must be presented to the converter

first. The voltage that represents zero scale point

must be input to the converter before the calibra-

tion step is initiated and must remain stable until

the step is complete. The DRDY output from the

converter will signal when the step is complete by

going low. After the zero scale point is calibrated,

the voltage representing the full scale point is in-

put to the converter and the second calibration

step is initiated. Again the voltage must remain

stable throughout the calibration step.

This two step calibration mode offers another cali-

bration feature.

After a two step calibration

Sequence

FS Cal

ZS Cal

SC2

SC1

CAL

Cal Type

Calibration Time

One Step

VREF

AGND

Self-Cal

3,145,655/f

1st Step

AIN

1,052,599/f

2nd Step

AIN

1,068,813/f

One Step

VREF

AIN

System Offset

2,117,389/f

System Offset

& System Gain

clk

* DRDY remains high throughout the calibration sequence. In Self-Cal mode (SC1 and SC2 low) DRDY

falls once the CS5501 or CS5503 has settled to the analog input. In all other modes DRDY falls

immediately after the calibration term has been determined.

Table 2. Calibration Control

VREF sys

Transducer

Analog

MUX

µC

CLK

DATA

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

CAL SC1 SC2

SDATA

SCLK

CS5501

CS5503

A0 A1

Signal

Conditioning

Circuitry

Figure 9. System Calibration

CS5501/CS5503

DS31F2

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