CS5501-SD datasheet(16/54 Pages) CIRRUS

16 / 54 page

provide data output in UART compatible format.

The baud rate of the SDATA output will be deter-

mined by the rate of the SCLK input. The data

which is output of the SDATA pin will be format-

ted such that it will contain two 11 bit data

packets. Each packet includes one start bit, eight

data bits, and two stop bits. The packet which car-

ries the most-significant-byte data will be output

first, with its lsb being the first data bit output

after the start bit.

In this mode, DRDY will occur every 1024 clock

cycles. If the serial port is not outputting a data

byte, DRDY will return high after 1020 clock cy-

cles and remain high for 4 clock cycles. DRDY

will then go low to indicate that an update to the

serial output port with a new 16 bit word has oc-

curred. To initiate a transmission from the port the

CS line must be taken low. Then SCLK, which is

an input in this mode, must transition from a high

to a low to latch the state of CS internal to the

CS5501. Once CS is recognized and latched as a

low, the port will begin to output data. Figure 7

details the timing for this output. CS can be re-

tu rned high before the end of the 11-bit

transmission and the transmission will continue

until the second stop bit of the first 11-bit packet

is output. The SDATA output will go into a high

impedance state after the second stop bit is output.

To obtain the second 11-bit packet CS must again

be brought low before DRDY goes high or the

second 11-bit data packet will be overwritten with

a serial port update. For the second 11-bit packet,

CS need only to go low for 50 ns; it need not be

latched by a falling edge of SCLK. Alternately,

the CS line can be taken low and held low until

both 11-bit data packets are output. This is the

preferred method of control as it will prevent los-

ing the second 11-bit data packet if the port is

updated. Some serial data rates can be quite slow

compared to the rate at which the CS5501 can up-

date its output port. A slow data rate will leave

only a short period of time to start the second 11-

bit packet if CS is returned high momentarily. If

CS is held low continuously (CS hard-wired to

DGND), the serial port will be updated only after

all 22 bits have been clocked out of the port.

Upon the completion of a transmission of the two

11-bit data packets the SDATA output will go into

a high impedance state. If at any time during

transmission the CS is taken back high, the cur-

rent 11-bit data packet will continue to be output.

At the end of the second stop bit of the data

packet, the SDATA output will go into a high im-

pedance state.

Linearity Performance

The CS5501/CS5503 delta-sigma converters are

like conventional charge-balance converters in

that they have no source of nonmonotonicity. The

devices therefore have no missing codes in their

transfer functions. See Figure 8 for a plot of the

SCLK (i)

SDATA (o)

DRDY (o)

CS (i)

Stop

Hi-Z

Start

B14 B15

Start

Figure 7. CS5501 Asynchronous (UART) Mode Timing

CS5501/CS5503

DS31F2

CS5501-SD 数据表(PDF) 16 Page - Cirrus Logic

CS5501-SD 数据表(HTML) 16 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

数据表下载