Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
18
2.4
Local Bus Pin Descriptions (31 pins)
Signal Name
Pin
Type
Description
LA[4:0]
28-32
I
Address Bus.
Five bits of address can directly address most of the
internal registers of the NET2272. A minimum of 1 address bit is required
to operate the NET2272, using an optional Register-Indirect mode. A
third addressing mode (multiplexed address and data) uses ALE with
LD[4:0] to provide 5 bits of register addressing.
ALE
53
I
Address Latch Enable.
When operating in Multiplexed Address and
Data mode, the 5-bit address bus is latched on the trailing (negative) edge
of ALE.
The NET2272 will automatically detect use of the ALE pin to
indicate use of multiplexed address and data on the LD[4:0] pins.
LD[15:0]
49, 47-43,
39-35,
23-19
I/O,
6mA
Data Bus. These pins serve as the input and output data bus for the local
CPU. In multiplexed address/data mode, ALE can be used with LD[4:0]
to provide 5-bits of address on the falling edge of ALE. In 16-bit mode,
the data bus is 16-bits wide.
IOR#
59
I
Read Strobe.
The local bus master asserts this signal during a read
transaction.
IOW#
60
I
Write Strobe. The local bus master asserts this signal during a write
transaction.
IRQ#
63
O,
12mA,
OD
Interrupt Request Output.
This signal interrupts the local processor
based on events selected in internal program registers. Since this pin is
open-drain, an external 1K pull-up resistor is required.
CS#
61
I
Chip Select. This signal enables access to registers within the NET2272.
Asserting this pin during suspend will cause the device to wake up.
Asserting this pin during RESET# holds the NET2272 in a low-power
mode by disabling the internal oscillator.
DMAWR#
34
I
DMA Write Strobe. The DMA bus master asserts this signal during a
DMA write transaction when split-bus DMA is selected.
DMARD#
50
I
DMA Read Strobe. The DMA bus master asserts this signal during a
DMA read transaction when split-bus DMA is selected
DREQ
62
O,
3mA,
TS
DMA Request.
This signal requests DMA transfers from an external
DMA controller. This output floats when the USB Host suspends the
device. The polarity of this signal is programmable.
DACK
51
I
DMA Acknowledge. Used to transfer data to/from the packet buffer in
response to DREQ. This pin is ignored unless the DMA DACK Enable bit
in the LOCCTL1 register is set.
The polarity of this signal is
programmable.
EOT
52
I
End of Transfer. This signal from an external DMA controller is used to
terminate a DMA transfer. The current word will be transferred, but no
additional transfers will be requested. EOT can be programmed to cause
an interrupt. The polarity of this signal is programmable.
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