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Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
28
4.6.2.1 Slow DMA Write Timing
In this mode, DREQ is de-asserted within T20 after the beginning of the write transaction. It is then re-asserted
within T21 after the end of the write transaction.
NetChip Technology; NET2272; Slow Mode DMA Write; 8/19/02; DMAWR.TD
D0
D1
0ns
25ns
50ns
75ns
100ns
125ns
DREQ
LD[15:0]
DACK#
IOW# (Optional)
EOT# (Optional)
4.6.2.2 Fast DMA Write Timing
In this mode, DREQ is de-asserted at the beginning of the write transaction. It is then re-asserted within T21 after
the end of the write transaction.
NetChip Technology; NET2272; Fast Mode DMA Write; 8/19/02; DMAWR_FAST.TD
D0
D2
D1
0ns
25ns
50ns
75ns
1
DREQ
LD[15:0]
DACK#
IOW# (Optional)
EOT# (Optional)
4.6.2.3 Burst DMA Write Timing
In this mode, DREQ remains asserted until the DMA transfer completes.
NetChip Technology; NET2272; Burst Mode DMA Write; 09/04/02; DMAWR_BURST.TD
D0
D2
D1
0ns
25ns
50ns
75ns
1
DREQ
LD[15:0]
DACK#
IOW# (Optional)
EOT# (Optional)
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