Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
26
4.6.1.1 Slow DMA Read Timing
In this mode, DREQ is de-asserted within T20 after the beginning of the read transaction. It is then re-asserted
within T21 after the end of the read transaction.
D0
NetChip Technology; NET2272; Slow Mode DMA Read; 08/19/02; DMARD.TD
D1
0ns
50ns
100ns
150ns
DREQ
DACK#
IOR# (Optional)
LD[15:0]
EOT# (Optional)
4.6.1.2 Fast DMA Read Timing
In this mode, DREQ is de-asserted at the beginning of the read transaction. It is then re-asserted either at the end of
the read transaction if the read enable width is greater than T21, or at T21 after the beginning of the read transaction
if the read enable width is less than T21.
D0
NetChip Technology; NET2272; Fast Mode DMA Read; 08/19/02; DMARD_FAST.TD
D2
D1
0ns
25ns
50ns
75ns
100ns
DREQ
DACK#
IOR# (Optional)
LD[15:0]
EOT# (Optional)
4.6.1.3 Burst DMA Read Timing
In this mode, DREQ remains asserted until the DMA transfer completes.
D0
NetChip Technology; NET2272; Burst Mode DMA Read; 09/04/02; DMARD_BURST.TD
D2
D1
0ns
25ns
50ns
75ns
100ns
DREQ
DACK#
IOR# (Optional)
LD[15:0]
EOT# (Optional)
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