Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
21
4
Local Bus Interface
4.1
Introduction
The Local Bus Interface allows the NET2272 to be easily interfaced with many generic processors and custom ASIC
interfaces. Both multiplexed and non-multiplexed buses are supported.
4.2
Register Addressing Modes
Several addressing methods are provided in the NET2272 in order to support various user architectures. These
modes are always active and nothing special needs to be done to use them. These modes act on a transaction-by-
transaction basis, allowing DMA and CPU to operate with inherently different bus architectures. For instance, the
CPU could operate with a multiplexed bus (using ALE to de-multiplex the Address/Data bus) while the DMA could
operate using a non-multiplexed Data bus.
4.2.1 Direct Address Mode
Direct Address Mode uses LA[4:0] to directly access the first 32 configuration registers.
4.2.2 Indirect Address Mode
Indirect Address mode uses registers REGADDRPTR (address 0x00) and REGDATA (address 0x01) to provide a
Command/Data interface to the NET2272 internal registers and buffers. All CPU transactions performed with
REGDATA will have their address sourced by REGADDRPTR. The local CPU first programs REGADDRPTR
with the desired register address, then reads or writes to REGDATA with the data intended for the register pointed
to by REGADDRPTR. This method of register addressing requires only 1 physical address bit (to access address
0x00 or address 0x01). All unused address bits of the NET2272 should be connected to ground. When all five
address bits are being used, this addressing method allows access to registers above address 1Fh.
4.2.3 Multiplexed Address Mode
Multiplexed Address mode uses the ALE pin to de-multiplex the desired address from the data bus. The NET2272
automatically detects the use of ALE and will use the address represented by LD[4:0] on the falling edge of ALE as
the address of the current transaction. This addressing mode is supported by several common microcontrollers.
ALE should be grounded if this mode is not used.
4.3
Control Signal Definitions
The control signals direct the flow of data across the local bus. A write transaction is performed by asserting CS#
and IOW#. The Address and Data must be valid on the trailing (rising) edge of IOW#. A read transaction is
performed by asserting CS# and IOR#.
4.4
Bus Width / Byte Alignment
The local bus supports 8 or 16-bit buses. In 8-bit mode, all configuration registers and the buffers are accessed one
byte at a time. A typical 8-bit application would connect the CPU address bits A[4:0] to the NET2272 address bus
LA[4:0].
In 16-bit mode, the configuration registers are still accessed a byte at a time, but the buffers are accessed a word at a
time. The Byte Swap bit in the LOCCTL configuration register determines whether the bytes are swapped as they
are being written into the buffer in 16-bit mode. This allows for connections to little or big endian processors. A
typical 16-bit application would connect the CPU address bits A[5:1] to the NET2272 address bus LA[4:0].
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