Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
30
4.6.5 DMA Performance
4.6.5.1 DMA Read; Slow Mode
•
DREQ to DACK: 5 nsec (depends on DMA controller)
•
DACK asserted to DREQ de-asserted (T20): 50 nsec
•
DREQ de-asserted to DREQ asserted (T25): 25 nsec
•
For an 8-bit bus, the maximum performance is:
1/80 nsec = 12.5 Mbytes/sec
•
For a 16-bit bus, the maximum performance is:
2/80 nsec = 25 Mbytes/sec
•
The actual throughput will be reduced if the DMA controller DREQ to DACK delay is longer than 5 nsec.
4.6.5.2 DMA Read; Fast Mode
•
DREQ to DACK: 5 nsec (depends on DMA controller)
•
Read Width (T22): 16 nsec
•
DACK de-asserted to DREQ asserted (T21): 35 nsec
•
For an 8-bit bus, the maximum performance is:
1/56 nsec = 17.8 Mbytes/sec
•
For a 16-bit bus, the maximum performance is:
2/56 nsec = 35.7 Mbytes/sec
•
The actual throughput will be reduced if the DMA controller DREQ to DACK delay is longer than 5 nsec.
4.6.5.3 DMA Read; Burst Mode
•
DMA Read Cycle time (T17): 35 nsec
•
For an 8-bit bus, the maximum performance is:
1/35 nsec = 28 Mbytes/sec
•
For a 16-bit bus, the maximum performance is:
2/35 nsec = 57 Mbytes/sec
4.6.5.4 DMA Write; Slow Mode
•
DREQ to DACK: 5 nsec (depends on DMA controller)
•
DACK asserted to DREQ de-asserted (T20): 50 nsec
•
DREQ de-asserted to DREQ asserted (T25): 25 nsec
•
For an 8-bit bus, the maximum performance is:
1/80 nsec = 12.5 Mbytes/sec
•
For a 16-bit bus, the maximum performance is:
2/80 nsec = 25 Mbytes/sec
•
The actual throughput will be reduced if the DMA controller DREQ to DACK delay is longer than 5 nsec.
4.6.5.5 DMA Write; Fast Mode
•
DREQ to DACK: 5 nsec (depends on DMA controller)
•
Write Width (T26): 5 nsec
•
DACK de-asserted to DREQ asserted (T21): 45 nsec
•
For an 8-bit bus, the maximum performance is:
1/55 nsec = 18 Mbytes/sec
•
For a 16-bit bus, the maximum performance is:
2/55 nsec = 36 Mbytes/sec
•
The actual throughput will be reduced if the DMA controller DREQ to DACK delay is longer than 5 nsec.
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