Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
27
4.6.2 DMA Write
For IN transfers (device to host), the local and host CPUs first arrange to transfer a block of data from local memory
to host memory. The local CPU programs the external DMA controller to transfer the desired number of bytes. The
NET2272 EP_TRANSFER register is also programmed with the desired transfer size (in bytes). The transfer size
programmed into the EP_TRANSFER register can span many packets, allowing a single DMA setup to transfer
multiple packets. The DMA Request signal (DREQ) is asserted anytime there is space available in the buffer. The
endpoint’s Max Packet Size register controls the maximum number of bytes transmitted to the host in a single
packet. A short packet will be sent if there are remaining bytes to be sent when all EP_TRANSFER bytes have
been written or when EOT has been asserted during the last DMA cycle.
The signals DREQ, DACK, IOW#, and EOT are used to control the transactions between the external DMA
controller and the NET2272. DREQ and DACK are minimally needed to exchange data with the NET2272 since
the direction (write) is established by the Endpoint Direction bit in the EP_CFG register. The mode of operation is
set by the DMA Control DACK bit in the DMAREQ register. If the DMA Control DACK bit is high, then both
DACK and IOW# are needed by the NET2272 for a DMA write. If the DMA Control DACK bit is low, then only
DACK is needed.
The local CPU programs the NET2272 DMAREQ register to associate the DMA with a NET2272 endpoint (either
Endpoint A or Endpoint B). Transfers occur only when the NET2272 requests them, after the DMA Request Enable
bit is set in the DMAREQ register.
As long as there is space available in the selected endpoint’s buffer, and there are still bytes to be transferred, the
NET2272 will request DMA transfers by asserting DREQ. The external DMA controller then requests the local bus
from the local CPU. After the DMA controller has been granted the bus, it drives DACK, IOW# (optional), and
MEMR# (to memory) to transfer a byte from memory to the endpoint’s buffer. For DMA slow mode, the NET2272
de-asserts DREQ within T20 after the start of the transaction while for DMA fast mode, the NET2272 de-asserts
DREQ at the beginning of the transaction. If there is still space in the buffer and there are more bytes to be
transferred, the NET2272 re-asserts DREQ.
The USB host sends an IN token to the NET2272 and starts an IN data transaction from the selected endpoint’s
buffer. The DMA transfers continue until EP_TRANSFER bytes have been transferred or EOT has been asserted.
The DMA Done Interrupt bit in the IRQSTAT0 register will be set for the following conditions:
•
The EOT pin is asserted during the last DMA transfer.
•
The EP_TRANSFER counter counts down to 0.
•
The local CPU writes a zero to the EP_TRANSFER register after the DMA has finished.
If DMA Burst Mode is selected, DREQ is asserted when there is space in the buffer and the DMA is enabled. It
remains asserted until the FIFO becomes full, the DMA is disabled, the EP_TRANSFER counter counts down to 0,
or the EOT pin is asserted.
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