Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
36
5.6.2.1 Control Read Transfer
A successful control read transfer from Control Endpoint 0 consists of the following:
Transaction
Stage
Packet Contents
# of bytes
Source
Setup
Setup Token
SETUP PID, address, endpoint, and CRC5
3
Host
Data
DATA0 PID, 8 data bytes, and CRC16
11
Host
Status
ACK
1
NET2272
Data (zero, one, or
more packets)
IN Token
IN PID, address, endpoint, and CRC5
3
Host
Data (1/0)
DATA PID, N data bytes, and CRC16
N+3
NET2272
Status
ACK
1
Host
Status
OUT Token
OUT PID, address, endpoint, and CRC5
3
Host
Data
DATA1 PID, zero length packet, and CRC5
3
Host
Status
ACK
1
NET2272
The Setup transaction is processed in the same way as for control write transfers.
During the Data transaction, zero, one or more data packets are read from the Endpoint 0 buffer. For each packet:
•
Interrupt bits are set and can interrupt the local CPU
•
The local CPU writes data to the buffer
•
If there is no data in the buffer, a NAK or zero length packet is returned to the host
•
The Host returns an ACK to the NET2272 if no error has occurred.
For a successful Status transaction, the Host sends a zero length data packet, and the NET2272 responds with an
ACK. A NAK or STALL can be returned if an error occurred.
5.6.2.2 Control Read Transfer Details
For control read transfers, the host first sends 8 bytes of setup information. The setup bytes are stored into an 8-byte
register bank that can be accessed from the local CPU. After the eight bytes have been stored into the setup registers,
the Setup Packet Interrupt bit is set. The local CPU then reads the 8-byte setup packet and prepares to respond to
the optional Data transactions. The number of bytes to be transferred in the Data transactions is specified in the
setup packet. When the setup packet is received, the Control Status Phase Handshake bit is automatically set. While
this bit is set, the control status phase will be acknowledged with a NAK, allowing the local CPU to prepare its
handshake response (ACK or STALL). Once the Control Status Phase Handshake bit is cleared, the ACK or
STALL handshake will be returned to the host.
During a control read operation, optional Data transactions can follow the Setup transaction. After the Setup
transaction, the local CPU can start writing the first byte of packet data into the Endpoint 0 buffer in anticipation of
the Data transaction. The Data In Token Interrupt bit is set at the beginning of each Data transaction. If there is
data in the Endpoint 0 buffer, it is returned to the host. If Endpoint 0 has no data to return, it returns either a zero
length packet (signaling that there is no more data available) or a NAK handshake (the data is not available yet).
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