Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
97
10.4.10
Local Bus DMA Read; Fast Mode
Operating Conditions: VDDC: 2.2-2.6V, VDDIO: 3.2-3.5V, TA = 0°C to 70°C, Output Load = 25pF
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
T20
Read enable true to DREQ false (2)
4
19
ns
T21
Read enable false to DREQ true
4
35
45
ns
T22
Data access time from read enable (1)
16
ns
T23
Data tri-state time from end of read enable
2
12
ns
T24
Width of EOT# pulse (3)
10
ns
T25
DREQ false to DREQ true
15
35
ns
(1) For non-split DMA mode, read enable is the occurrence of DACK# and optionally, IOR#. For split DMA mode,
read enable is the occurrence of DACK# and optionally, DMARD#.
(2) The minimum value is only guaranteed if the DMA Request Enable bit in the DMAREQ register is set.
(3) EOT#, DACK#, and optionally, IOR# or DMARD# must all be true for at least T24 for proper recognition of the
EOT# pulse.
(4) A recovery time of 2 nsec is required between the de-assertion of DMA read enable and the assertion of an I/O
read enable.
T20
T21
T25
T20
T22
T23
T22
T23
T24
D0
D1
0ns
50ns
100ns
150ns
200ns
DREQ
DACK#
IOR# (Optional)
LD[15:0]
EOT# (Optional)
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