Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
35
5.6.2 Control Write Transfer Details
For control write transfers, the host first sends 8 bytes of setup information. The setup bytes are stored into an 8-byte
register bank that can be accessed by the local CPU. After the eight bytes have been stored into the setup registers,
the Setup Packet Interrupt bit is set. The local CPU then reads the 8-byte setup packet and prepares to respond to
the optional Data transactions. The number of bytes to be transferred in the Data transactions is specified in the
setup packet. When the setup packet is received, the Control Status Phase Handshake bit is automatically set in
anticipation of the control status phase. While this bit is set, the control status phase will be acknowledged with a
NAK, allowing the local CPU to prepare its handshake response (ACK or STALL). Once the Control Status Phase
Handshake bit is cleared and the OUT buffer is empty, the ACK or STALL handshake will be returned to the host.
Waiting for the OUT FIFO to become empty prevents another Control Write from corrupting the current packet data
in the FIFO.
During a control write operation, optional Data transactions can follow the Setup transaction. The Data Out Token
Interrupt bit is set at the beginning of each Data transaction. The bytes corresponding to the Data transaction are
stored into the Endpoint 0 packet buffer. If the buffer fills up and another byte is transferred from the host, the
NET2272 will return a NAK handshake to the host, signaling that the data could not be accepted.
If a packet is not successfully received (NAK or Timeout status), the Data Packet Received Interrupt bit will not be
set, and the data will be automatically flushed from the buffer. The host will re-send the same packet again. This
process is transparent to the local CPU.
If the local CPU has stalled this endpoint by setting the Endpoint Halt bit, the NET2272 will not store any data into
the buffer, and will respond with a STALL acknowledge to the host. There will not be a Status transaction in this
case.
The local CPU can either poll the Data Packet Received Interrupt bit, or enable it as an interrupt, and then read the
packet from the buffer when the interrupt occurs. If the host tries to write more data than was indicated in the setup
packet, then the local CPU should set the Endpoint Halt bit for Endpoint 0. In this case there will not be a status
stage from the host.
After all of the optional Data transaction packets have been received, the host will send an IN token, signifying the
Status transaction. The Control Status Interrupt bit is set after the IN token of the Status transaction has been
received. Until the Control Status Phase Handshake bit is cleared by the local CPU and the OUT buffer is empty,
the NET2272 will respond to the Status transaction with NAKs, indicating that the device is still processing the
setup command. When the Control Status Phase Handshake bit has been cleared by the local CPU and the firmware
has emptied the data form the OUT buffer, the NET2272 will respond with a zero length data packet (transfer OK)
or STALL (device had an error).
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