Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
56
41h
Indirect Only
SETUP1
Setup byte 1
42h
Indirect Only
SETUP2
Setup byte 2
43h
Indirect Only
SETUP3
Setup byte 3
44h
Indirect Only
SETUP4
Setup byte 4
45h
Indirect Only
SETUP5
Setup byte 5
46h
Indirect Only
SETUP6
Setup byte 6
47h
Indirect Only
SETUP7
Setup byte 7
8.4
Main Control Registers
8.4.1 (Address 00h; REGADDRPTR) Indirect Register Address Pointer
Bits
Description
Read
Write
Default
Value
7
Reserved.
0
No
0
6:0
Register Address. Register Address Pointer used for indirect register addressing.
Yes
Yes
0
8.4.2 (Address 01h; REGDATA) Indirect Register Data
Bits
Description
Read
Write
Default
Value
15:0
Register Data. Register Data port for indirect register addressing. For 8-bit bus
widths, data is transferred on bits [7:0]. For 16-bit buffer accesses, data is transferred
on bits [15:0].
Yes
Yes
0
8.4.3 (Address 02h; IRQSTAT0) Interrupt Status Register (low byte)
Bits
Description
Read
Write
Default
Value
7
SOF Interrupt. This bit indicates when a start-of-frame packet has been received by
the NET2272. Writing a 1 clears this status bit.
Yes
Yes/CLR
0
6
DMA Done Interrupt. For IN endpoints, this bit indicates that EOT# has been
asserted, the EP_TRANSFER counter reaches zero during a DMA, or the
corresponding EP_TRANSFER counter is loaded with a 0. For OUT endpoints, this
bit indicates that EOT# has been asserted, or that a short packet has been received
and the endpoint buffers have gone empty. Writing a 1 clears this status bit. This bit
is set independently of the corresponding interrupt enable bit.
Yes
Yes/CLR
0
5
Setup Packet Interrupt. This bit is set when a setup packet has been received from
the host. Writing a 1 clears this status bit.
Yes
Yes/CLR
0
4
Virtualized Endpoint Interrupt. This bit is set when one of the Virtual Endpoint
interrupts is set.
Yes
No
0
3
Endpoint C Interrupt. This bit conveys the interrupt status for Endpoint C. When
set, Endpoint C’s interrupt status register should be read to determine the cause of the
interrupt. This bit is set independently of the interrupt enable bit.
Yes
No
0
2
Endpoint B Interrupt. This bit conveys the interrupt status for Endpoint B. When
set, Endpoint B’s interrupt status register should be read to determine the cause of the
interrupt. This bit is set independently of the interrupt enable bit.
Yes
No
0
1
Endpoint A Interrupt. This bit conveys the interrupt status for Endpoint A. When
set, Endpoint A’s interrupt status register should be read to determine the cause of the
interrupt. This bit is set independently of the interrupt enable bit.
Yes
No
0
0
Endpoint 0 Interrupt. This bit conveys the interrupt status for Endpoint 0. When
set, Endpoint 0’s interrupt status register should be read to determine the cause of the
interrupt. This bit is set independently of the interrupt enable bit.
Yes
No
0
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