Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
58
8.4.6 (Address 1Ch; DMAREQ) DMA Request Control Register
Bits
Description
Read
Write
Default
Value
7
DMA Buffer Valid. When clear, the buffer will not be automatically validated at
the end of a DMA transfer. When set, the buffer is automatically validated at the end
of a DMA if EOT is asserted. This bit only applies to IN endpoints.
Yes
Yes
0
6
DMA Request. This status bit reflects the state of the DREQ output pin, and allows a
CPU on the local bus to monitor DMA transfers.
Yes
No
0
5
DMA Request Enable. Writing a 1 to this bit enables the NET2272 to start
requesting DMA cycles from a DMA controller on the local bus. If the EOT input is
asserted, or the EP_TRANSFER counter reaches zero, or a short OUT packet is
received and the endpoint buffer becomes empty, this bit is automatically reset. A
CPU on the local bus may also explicitly reset this bit to terminate a DMA transfer.
If the CPU writes a 0 to the EP_TRANSFER0 register of the endpoint selected by
Page Select, this bit is cleared. This bit can be read to determine whether a DMA
transfer is still in progress.
Yes
Yes
0
4
DMA Control DACK. When clear, only DACK is used to perform DMA read and
write transactions. When set, IOR# and IOW# (or DMARD# and DMAWR# for
split mode DMA) control signals are used with DACK to perform DMA read and
write transactions.
Yes
Yes
0
3
EOT Polarity. When clear, the EOT input pin is active low. When set, the EOT
input pin is active high.
Yes
Yes
0
2
DACK Polarity. When clear, the DACK input pin is active low. When set, the
DACK input pin is active high.
Yes
Yes
0
1
DREQ Polarity. When clear, the DREQ output pin is active low. When set, the
DREQ output pin is active high.
Yes
Yes
1
0
DMA Endpoint Select. This field determines which endpoint is being accessed
during a DMA channel transfer.
Value
Endpoint used during DMA
0
Endpoint A
1
Endpoint B
Yes
Yes
0
8.4.7 (Address 1Dh; SCRATCH) Scratchpad Register
Bits
Description
Read
Write
Default
Value
7:0
SCRATCH. General-purpose scratchpad register.
Yes
Yes
5Ah
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
