Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
60
8.4.10 (Address 22h; LOCCTL) Local Bus Control Register
Bits
Description
Read
Write
Default
Value
7:6
Buffer Configuration. Buffer configuration for endpoints A and B. For example, if
value 01 is selected, Endpoint A will be allocated a single buffer with buffer size set
to 1024 bytes, while Endpoint B will be allocated a double buffer with each buffer
size set to 512 bytes. Actual packets sent/received can be less than or equal to the
EP_MAXPKT size for the selected endpoint. The EP_MAXPKT size must be less
than or equal to the allocated buffer size.
Value
EP_A
EP_B
00
512 db *
512 db
01
1024
512 db
10
1024
1024
11
1024 db
Disabled
* "db" means double buffered. All values shown in bytes.
Yes
Yes
00
5
Byte Swap. When clear, local data bus LD[15:0] is connected to the endpoint buffer
with no byte swapping. When set, the two bytes of a 16-bit data bus are swapped
before connecting to the endpoint buffer.
Yes
Yes
0
4
DMA Split Bus Mode. When clear, I/O and DMA accesses share the same data bus.
When set, I/O accesses to the configuration registers or buffers use LD[7:0], and
DMA accesses to the buffers use LD[15:8], thus splitting the data bus for CPU and
DMA accesses.
Yes
Yes
0
3:1
Local Clock Output. This field controls the frequency of the LCLKO pin.
Value
Frequency
000
0 (off)
001
3.75 MHz
010
7.5 MHz (default)
011
15 MHz
100
30 MHz
101
60 MHz
110
Reserved
111
Reserved
Yes
Yes
2
0
Data Width. This field controls the width of the local data bus for EP_DATA
accesses to endpoint buffers. Write to this register using the lower 8 bits of the data
bus to switch to 16-bit mode. This bit does not affect accesses to any other registers.
Value
Width
0
8 bits
1
16 bits
Yes
Yes
0
8.4.11 (Address 23h; CHIPREV_LEGACY) Legacy Silicon Revision Register
Bits
Description
Read
Write
Default
Value
7:0
Legacy Chip Revision. This register returns a legacy silicon revision number for use
by Net2270 firmware.
Yes
No
‘h40
Note: The chip revision is encoded as a 2-digit BCD value. The most significant digit is the major revision number,
and the least significant digit is the minor revision number.
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