M58LR128HT datasheet(8/112 Pages) STMICROELECTRONICS

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Description

M58LR128HT, M58LR128HB

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Description

The M58LR128HT/B are 128 Mbit (8 Mbit ×16) non-volatile Flash memories. They may be

erased electrically at block level and programmed in-system on a Word-by-Word basis using

a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the

Input/Output pins. An optional 9V VPP power supply is provided to speed up factory

programming.

The devices feature an asymmetrical block architecture. The M58LR128HT/B have an array

of 131 blocks, and are divided into 8 Mbit banks. There are 15 banks each containing 8 main

blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords

and 7 main blocks of 64 KWords.

The Multiple Bank Architecture allows Dual Operations, while programming or erasing in

one bank, read operations are possible in other banks. Only one bank at a time is allowed to

be in program or erase mode. It is possible to perform burst reads that cross bank

boundaries. The bank architecture is summarized in Table 2, and the memory map is shown

in Figure 3. The Parameter Blocks are located at the top of the memory address space for

the M58LR128HT, and at the bottom for the M58LR128HB.

Each block can be erased separately. Erase can be suspended, in order to perform a

program or read operation in any other block, and then resumed. Program can be

suspended to read data at any memory location except for the one being programmed, and

then resumed. Each block can be programmed and erased over 100,000 cycles using the

supply voltage VDD. There is a Buffer Enhanced Factory programming command available

to speed up programming.

Program and erase commands are written to the Command Interface of the memory. An

internal Program/Erase Controller takes care of the timings necessary for program and

erase operations. The end of a program or erase operation can be detected and any error

conditions identified in the Status Register. The command set required to control the

memory is consistent with JEDEC standards.

The device supports Synchronous Burst Read and Asynchronous Read from all blocks of

the memory array; at power-up the device is configured for Asynchronous Read. In

Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to

54 MHz. The Synchronous Burst Read operation can be suspended and resumed.

The device features an Automatic Standby mode. When the bus is inactive during

Asynchronous Read operations, the device automatically switches to the Automatic Standby

mode. In this condition the power consumption is reduced to the standby value and the

outputs are still driven.

The M58LR128HT/B features an instant, individual block locking scheme that allows any

block to be locked or unlocked with no latency, enabling instant code and data protection. All

blocks have three levels of protection. They can be locked and locked-down individually

preventing any accidental programming or erasure. There is an additional hardware

protection against program and erase. When VPP ≤VPPLK all blocks are protected against

program or erase. All blocks are locked at power-up.

The device includes 17 Protection Registers and 2 Protection Register locks, one for the first

Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection

Registers of 128 bits each. The first Protection Register is divided into two segments: a 64

bit segment containing a unique device number written by ST, and a 64 bit segment One-

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