M58LR128HT datasheet(46/112 Pages) STMICROELECTRONICS

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Read modes

M58LR128HT, M58LR128HB

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7.2

Synchronous Burst Read mode

In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It

is possible to perform burst reads across bank boundaries.

Synchronous Burst Read mode can only be used to read the memory array. For other read

operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single

Synchronous Read or Asynchronous Random Access Read must be used.

In Synchronous Burst Read mode the flow of the data output depends on parameters that

are configured in the Configuration Register.

A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock

Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip

Enable, whichever occurs last. Addresses are internally incremented and data is output on

each data cycle after a delay which depends on the X latency bits CR13-CR11 of the

Configuration Register.

The number of Words to be output during a Synchronous Burst Read operation can be

configured as 4 Words, 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0).

The data can be configured to remain valid for one or two clock cycles (Data Output

Configuration bit CR9).

The order of the data output can be modified through the Wrap Burst bit in the Configuration

boundary (Wrap) or overcome the boundary (No Wrap).

The WAIT signal may be asserted to indicate to the system that an output delay will occur.

This delay will depend on the starting address of the burst sequence and on the burst

configuration.

WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 Word

burst. It is only de-asserted when output data are valid or when G is at VIH. In Continuous

Burst Read mode a WAIT state will occur when crossing the first 16 Word boundary. If the

starting address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration

has no impact on the output sequence.

The WAIT signal can be configured to be active Low or active High by setting CR10 in the

Configuration Register.

See Table 24: Synchronous Read AC characteristics, and Figure 11: Synchronous Burst

Read AC waveforms, for details.

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