M58LR128HT datasheet(25/112 Pages) STMICROELECTRONICS

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M58LR128HT, M58LR128HB

Command interface

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4.10.2

Program and Verify phase

The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write

Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until

the Write Buffer is full (32 Words). To program less than 32 Words, the remaining Words

should be programmed with FFFFh.

Three successive steps are required to issue and execute the Program and Verify Phase of

the command.

Use one Bus Write operation to latch the Start Address and the first Word to be

programmed. The Status Register Bank Write Status bit SR0 should be read to check

that the P/E.C. is ready for the next Word.

Each subsequent Word to be programmed is latched with a new Bus Write operation.

The address must remain the Start Address as the P/E.C. increments the address

location.If any address that is not in the same block as the Start Address is given, the

Program and Verify Phase terminates. Status Register bit SR0 should be read between

each Bus Write cycle to check that the P/E.C. is ready for the next Word.

Once the Write Buffer is full, the data is programmed sequentially to the memory array.

After the program operation the device automatically verifies the data and reprograms if

necessary.

The Program and Verify phase can be repeated, without re-issuing the command, to

program additional 32 Word locations as long as the address remains in the same block.

Finally, after all Words, or the entire block have been programmed, write one Bus Write

operation to any address outside the block containing the Start Address, to terminate

Program and Verify Phase.

Status Register bit SR0 must be checked to determine whether the program operation is

finished. The Status Register may be checked for errors at any time but it must be checked

after the entire block has been programmed.

4.10.3

Exit phase

Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has exited the Buffer

Enhanced Factory Program operation and returned to Read Status Register mode. A full

Status Register check should be done to ensure that the block has been successfully

programmed. See the section on the Status Register for more details.

For optimum performance the Buffer Enhanced Factory Program command should be

limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the

internal algorithm will continue to work properly but some degradation in performance is

possible. Typical program times are given in Table 17.

See Appendix C, Figure 27: Buffer Enhanced Factory Program flowchart and pseudocode,

for a suggested flowchart on using the Buffer Enhanced Factory Program command.

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