M58LR128HT datasheet(38/112 Pages) STMICROELECTRONICS

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Configuration Register

M58LR128HT, M58LR128HB

38/112

Configuration Register

The Configuration Register is used to configure the type of bus access that the memory will

perform. Refer to Read Modes section for details on read operations.

The Configuration Register is set through the Command Interface using the Set

Configuration Register command. After a reset or power-up the device is configured for

asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 11

They specify the selection of the burst length, burst type, burst X latency and the read

operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.

6.1

Read Select bit (CR15)

The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous

Read operations.

When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read

Select bit is set to ’0’, read operations are synchronous.

Synchronous Burst Read is supported in both parameter and main blocks and can be

performed across banks.

On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.

6.2

X-Latency bits (CR13-CR11)

The X-Latency bits are used during Synchronous Read operations to set the number of

clock cycles between the address being latched and the first data becoming available. Refer

to Figure 5: X-Latency and data output configuration example.

For correct operation the X-Latency bits can only assume the values in Table 11:

Configuration Register.

Table 10 shows how to set the X-Latency parameter, taking into account the speed class of

the device and the Frequency used to read the Flash memory in Synchronous mode.

Table 10.

X-Latency settings

fmax

tKmin

X-Latency min

30 MHz

33 ns

40 MHz

25 ns

54 MHz

19 ns

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