M58LR128HT datasheet(90/112 Pages) STMICROELECTRONICS

90 / 112 page

Common Flash Interface

M58LR128HT, M58LR128HB

90/112

The variable P is a pointer which is defined at CFI offset 015h.

Bank Regions. There are two Bank Regions, see Table 30 to Table 31.

(P+30)h = 13Ah

01h

(P+30)h = 13Ah

01h

Bank Region 1 (Erase Block Type 1): BIts per

cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

(P+31)h = 13Bh

03h

(P+31)h = 13Bh

03h

Bank Region 1 (Erase Block Type 1): Page

mode and Synchronous mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+32)h = 13Ch

06h

Bank Region 1 Erase Block Type 2 Information

Bits 0-15: n+1 = number of identical-sized erase

blocks

Bits 16-31: n×256 = number of bytes in erase

block region

(P+33)h = 13Dh

00h

(P+34)h = 13Eh

00h

(P+35)h = 13Fh

02h

(P+36)h = 140h

64h

Bank Region 1 (Erase Block Type 2)

Minimum block erase cycles × 1000

(P+37)h = 141h

00h

(P+38)h = 142h

01h

Bank Regions 1 (Erase Block Type 2): BIts per

cell, internal ECC

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

(P+39)h = 143h

03h

Bank Region 1 (Erase Block Type 2): Page

mode and Synchronous mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

Table 40.

Bank and Erase block region 1 information (continued)

M58LR128HT (top)

M58LR128HB

(bottom)

Description

Offset

Data

Offset

Data

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