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M58LR128HT 数据表(PDF) 41 Page - STMicroelectronics |
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M58LR128HT 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 112 page  M58LR128HT, M58LR128HB Configuration Register 41/112 Table 11. Configuration Register Bit Description Value Description CR15 Read Select 0 Synchronous Read 1 Asynchronous Read (Default at power-on) CR14 Reserved CR13-CR11 X-Latency 010 2 clock latency(1) 1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported. 011 3 clock latency 100 4 clock latency 101 5 clock latency 110 6 clock latency 111 7 clock latency (default) Other configurations reserved CR10 Wait Polarity 0 WAIT is active Low 1 WAIT is active High (default) CR9 Data Output Configuration 0 Data held for one clock cycle 1 Data held for two clock cycles (default)(1) CR8 Wait Configuration 0 WAIT is active during WAIT state 1 WAIT is active one data cycle before WAIT state(1) (default) CR7 Burst Type 0Reserved 1 Sequential (default) CR6 Valid Clock Edge 0 Falling Clock edge 1 Rising Clock edge (default) CR5-CR4 Reserved CR3 Wrap Burst 0Wrap 1 No Wrap (default) CR2-CR0 Burst Length 001 4 Words 010 8 Words 011 16 Words 111 Continuous (default) |
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