ADIN1110BCPZ-R7 datasheet(41/107 Pages) AD

41 / 107 page

Data Sheet

ADIN1110

MAC SPI

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Rev. B | 41 of 107

7. Write MDIOACC6 with MDIO_DATA = the address of Register

XYZ and TRDONE = 0x0.

8. Write MDIOACC7 with the write data for Register XYZ,

MDIO_OP = 0x1, and TRDONE = 0x0.

9. Host polls MDIOACC7. TRDONE = 0x1 to verify that all write

data operations are complete.

Example burst read starting from Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = the address of the Regis-

ter XYZ, MDIO_OP = 0x0(ADDR), and TRDONE = 0x0

2. Write MDIOACC1 with MDIO_OP = 0x2(INC_RD) and

TRDONE = 0x0.

3. Write MDIOACC2 with MDIO_OP = 0x2(INC_RD) and

TRDONE = 0x0.

4. Write MDIOACC3 with MDIO_OP = 0x2(INC_RD) and

TRDONE = 0x0.

5. Write MDIOACC4 with MDIO_OP = 0x2(INC_RD) and

TRDONE = 0x0.

6. Write MDIOACC5 with MDIO_OP = 0x2(INC_RD) and

TRDONE = 0x0.

7. Write MDIOACC6 with MDIO_OP = 0x2(INC_RD) and

TRDONE = 0x0.

8. Write MDIOACC7 with MDIO_OP = 0x2(INC_RD) and

TRDONE = 0x0.

9. Poll MDIOACC7. TRDONE = 1 to verify that all read data

operations are complete.

10. Read MDIOACC1. MDIO_DATA, reflects the content of Register

XYZ.

11. Read MDIOACC2. MDIO_DATA, reflects the content of register

at address XYZ. ADDR + 1.

12. Read MDIOACC3. MDIO_DATA, reflects the content of register

at address XYZ. ADDR + 2.

13. Read MDIOACC4. MDIO_DATA, reflects the content of register

at address XYZ. ADDR + 3.

14. Read MDIOACC5. MDIO_DATA, reflects the content of register

at address XYZ. ADDR + 4.

15. Read MDIOACC6. MDIO_DATA, reflects the content of register

at address XYZ. ADDR + 5.

16. Read MDIOACC7. MDIO_DATA, reflects the content of register

at address XYZ. ADDR + 6.

Example of Clause 22 write of Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = write data,

MDIO_DEV_AD = the address of the Register XYZ,

MDIO_PRTAD = 0x1, MDIO_OP = 0x1(WR), MDIO_ST =

0x1(Clause 22), and TRDONE = 0x0.

2. Poll MDIOACC0. TRDONE= 0x1 to determine that the write

data operation is complete.

Example of Clause 22 read of Register XYZ:

1. Write MDIOACC0 with MDIO_DEV_AD = the address of the

MDIO_ST = 0x1(Clause 22), and TRDONE = 0x0.

2. Poll MDIOACC0. TRDONE = 0x1 to determine that the read

operation is complete. MDIO_DATA reflects the contents of

MDIO Register XYZ.

Example of Clause 22 write and read back of Register XYZ:

1. Write MDIOACC0 with MDIO_DATA = write data,

MDIO_DEV_AD = the address of the Register XYZ,

MDIO_PRTAD = 0x1, MDIO_OP = 0x1(WR), MDIO_ST =

0x1(Clause 22), and TRDONE = 0x0.

2. Write MDIOACC1 with MDIO_DEV_AD = the address of the

MDIO_ST = 0x1(Clause 22), and TRDONE = 0x0.

3. Poll MDIOACC1. TRDONE = 0x1 to determine that the read

operation is complete. MDIO_DATA reflects the contents of

MDIO Register XYZ.

MDIO PHY Address Determination

The MDIO PHY address for the ADIN1110 PHY is 0x1.

PHY Registers Contents

The PHY registers provide access to control and status information

in the management registers.

The registers of the PHY Clause 45 register map are made up of

four device address groupings (see Table 36) based on the MDIO

manageable device (MMD). Within each device address space,

IEEE standard registers are located in register addresses between

0x0000 and 0x7FFF, and vendor specific registers are located in

Table 36. Clause 45 Register Groupings

Device Address

MMD Name

0x01

Physical medium attachment (PMA)/physical medium

dependent (PMD)

0x03

Physical coding sublayer (PCS)

0x07

Autonegotiation

0x1E

Vendor Specific 1

Clause 45 can access to up to 32 PHYs consisting of up to 32

MMDs through a single MDIO interface.

The default value of some of the registers are determined by the

value of the hardware configuration pins, which are read just after

the RESET pin is deasserted. In these cases, the reset value

in the register table is listed as pin dependent, which allows the

default operation of the ADIN1110 to be configured without having

to write to it over the SPI. This method is useful in unmanaged

applications where the desired operation of the PHY is configured

from the hardware configuration pins without any software interven-

tion. For unmanaged applications, do not configure the PHY to

enter software power-down mode after reset to ensure that the PHY

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