ADIN1110BCPZ-R7 datasheet(47/107 Pages) AD

47 / 107 page

Data Sheet

ADIN1110

REGISTERS

analog.com

Rev. B | 47 of 107

PHY Identification Register

Address: 0x01, Reset: 0x0283BC91, Name: PHYID

Table 40. Bit Descriptions for PHYID

Bits

Bit Name

Description

Reset

Access

[31:10]

OUI

Organizationally Unique Identifier (Bits[23:2]). The 22 bits in the OUI field correspond to the 22 most

significant bits of the manufacturer’s assigned 24-bit organizationally unique identifier (OUI). The OUI is

arranged into the PHYID register such that OUI Bit 2 is located at PHYID Bit 31, and OUI Bit 23 is located at

PHYID Bit 10.

0xA0EF

[9:4]

MODEL

Manufacturer’s Model Number. The manufacturer’s model number is used to identify the device.

0x9

[3:0]

REVISION

Manufacturer’s Revision Number. The manufacturer’s product revision number is used to indicate a revision

level of the device.

0x1

Supported Capabilities Register

Address: 0x02, Reset: 0x000006C3, Name: CAPABILITY

Table 41. Bit Descriptions for CAPABILITY

Bits

Bit Name

Description

Reset

Access

[31:11]

RESERVED

Reserved.

0x0

TXFCSVC

Transmit Frame Check Sequence Validation Capability. Indicates the ability to validate the FCS appended by

and received from the SPI host. When this bit is set it also indicates the ability of the MAC to be configured to

accept egress frames with padding and FCS appended by the SPI host, and send ingress frames to the SPI

host with the received FCS.

0x1

0: transmit FCS validation is not supported.

1: transmit FCS validation is supported.

IPRAC

Indirect PHY Register Access Capability. Indicates if PHY registers are directly accessible within the SPI

0x1

0: PHY registers are not indirectly accessible.

1: PHY registers are indirectly accessible.

DPRAC

Direct PHY Register Access Capability. Indicates if PHY registers are directly accessible within the SPI

0x0

0: PHY registers are not directly accessible.

1: PHY registers are directly accessible.

CTC

Cut Through Capability. Indicates if the MAC-PHY device supports cut through transfer of frames through the

MAC-PHY to and from the network.

0x1

0: cut through not supported.

1: cut through supported.

FTSC

Frame Time Stamp Capability. Frame Time Stamp Capability. Indicates if the MAC-PHY device supports the

capturing of IEEE 1588 time stamps on frame receive from or transmit to the network.

0x1

1: IEEE 1588 time stamp capture on frame Tx/Rx is supported.

0: IEEE 1588 time stamp capture on frame Tx/Rx is not supported.

AIDC

Address Increment Disable Capability. Indicates if the MAC-PHY device supports the disabling of the

automatic post-incrementing of the register address in control command reads and writes through the AID bit

in the control command header. Address increment disable is not supported. This field is only used with the

OPEN Alliance SPI protocol.

0x0

SEQC

Tx Data Chunk Sequence and Retry Capability. Indicates if the MAC-PHY supports monitoring the SEQ bit

sent by the SPI host in the Tx data chunk header and the retry of Tx data chunks. This field is only used with

the OPEN Alliance SPI protocol.

0x0

1: Tx data chunk sequence and retry is supported.

0: Tx data chunk sequence and retry is not supported.

ADIN1110BCPZ-R7 数据表(PDF) 47 Page - Analog Devices

ADIN1110BCPZ-R7 数据表(HTML) 47 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载