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ADIN1110BCPZ-R7 数据表(PDF) 51 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 51 Page - Analog Devices |
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51 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 51 of 107 Table 45. Bit Descriptions for STATUS0 (Continued) Bits Bit Name Description Reset Access 7 PHYINT PHY Interrupt for Port 1. Host software must read the MDIO Interrupt Status registers (PhySubsysIrqStatus or CrsmIrqStatus) to determine the source of the interrupt. On exiting power-on reset or pin reset, this bit asserts, but this field is masked from asserting an interrupt by default. 0x0 R 6 RESETC Reset Complete. This bit is set when the MAC-PHY reset is complete and ready for configuration. When set, it generates a non-maskable interrupt assertion on IRQn to alert the SPI host. Additionally, setting the RESETC bit also sets EXST = 1 in the first Rx footer, or until this bit is cleared by action of the SPI host writing a 1.all Rx footers until this bit is cleared by action of the SPI host writing a 1, or this bit is masked. 0x1 R/W1C 5 HDRE Header Error. When set, this bit indicates that the MAC-PHY has detected an invalid header received from the SPI host. The invalid header is due to a parity check error. This field is only used with the OPEN Alliance SPI protocol. 0x0 R/W1C 4 LOFE Loss of Frame Error. When set, this bit indicates that the MAC-PHY has detected an early deassertion of CS before the expected end of a data chunk or command control transaction. Note that this bit also asserts if CDPE asserts. 0x0 R/W1C 3 RXBOE Receive Buffer Overflow Error. When set, this bit indicates that the receive buffer (from the network) has overflowed and receive frame data was lost. 0x0 R/W1C 2 TXBUE Host Tx FIFO Under Run Error. This error can only assert when cut through from the host is enabled. The host software must ensure this bit never asserts by writing frame data to the MAC at a rate greater than 10 Mbps.If an under run error occurs, transmit of the current packet stops. 0x0 R/W1C 1 TXBOE Host Tx FIFO Overflow. The host software must ensure this bit never asserts by checking the space available in the Tx FIFO before writing to the Tx FIFO. If using the OPEN Alliance SPI Data protocol, the space in the Tx FIFO is indicated in the TXC field of the Rx footer. If using the Generic SPI protocol, the TX_SPACE register indicates the remaining space in the Tx FIFO. If the host Tx FIFO overflows, the frame being written is dumped and software may chose to resend the entire frame. Writes to the FIFO commence at the next SOF. There is always room for more than one frame in the Host Tx FIFO as it is 4 kB (or greater) in size. Therefore, a frame currently transmitting is interrupted by an overflow on the write side of the FIFO. 0x0 R/W1C 0 TXPE Transmit Protocol Error. When set, this bit indicates that a Tx data chunk protocol error occurred. Data chunk received with DV = 1 but without a prior SV = 1. Data chunk received with SV = 1 but with no EV = 1 (repeated SV = 1 received). When using the generic SPI protocol, this bit indicates that the previous frame was not fully written. A write of the TX_FSIZE register was detected, but the MAC still expects further writes to the Tx register related to the previous frame size written to the TX_FSIZE register. 0x0 R/W1C Status Register 1 Address: 0x09, Reset: 0x00000000, Name: STATUS1 Table 46. Bit Descriptions for STATUS1 Bits Bit Name Description Reset Access [31:13] RESERVED Reserved. 0x0 R/W1C 12 TX_ECC_ERR ECC Error on Reading the Frame Size from a Tx FIFO. An uncorrectable ECC error was detected on a read of the size field from the Tx FIFO. The FIFO is automatically cleared and the frame associated with the ECC error and any other frames in the Tx FIFO are lost or dropped. 0x0 R/W1C 11 RX_ECC_ERR ECC Error on Reading the Frame Size from an Rx FIFO. An uncorrectable ECC error was detected on a reading the frame size field from an Rx FIFO. The FIFO is automatically cleared and the frame associated with the ECC error and other frames in the Rx FIFO are not lost or dropped. 0x0 R/W1C 10 SPI_ERR Detected an Error on an SPI Transaction. When using the generic SPI protocol, this field indicates that a CRC error was detected. This field is not used with the OPEN Alliance Protocol. See HDRE and CDPE in the Status Register 0 section for OPEN Alliance SPI errors. 0x0 R/W1C 9 RESERVED Reserved. 0x0 R/W1C 8 P1_RX_IFG_ERR Rx MAC Interframe Gap Error. If the IFG is too short, the frame is dropped on receive. The threshold used for measuring the IFG on receive can be set in the P1_RX_IFG register. 0x0 R/W1C [7:6] RESERVED Reserved. 0x0 R 5 P1_RX_RDY_HI Port1 Rx Ready High Priority. Indicates that there is a high priority frame available. This field does not drive the interrupt pin. This field is only used with the generic SPI protocol on LES. 0x0 R |
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