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ADIN1110BCPZ-R7 数据表(PDF) 55 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 55 Page - Analog Devices |
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55 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 55 of 107 Table 56. Bit Descriptions for MDIOACCn Bits Bit Name Description Reset Access 31 MDIO_TRDONE Transaction Done. This bit must be written to 0 by the SPI host to initiate an MDIO transaction. The MAC-PHY sets this bit to 1 when the MDIO transaction has completed. 0x1 R/W 30 MDIO_TAERR Turnaround Error. The MAC-PHY sets this bit to 1 when a turnaround error occurs during the MDIO transaction. If this occurs, the contents of the data field for read and read-post-increment-address operations is ignored. 0x0 R [29:28] MDIO_ST Start of Frame. This field selects between Clause 45 and Clause 22 MDIO access. 0x0 R/W 01: Clause 22 00: Clause 45 [27:26] MDIO_OP Operation Code. 0x3 R/W 00: MD address command. 01: write command. 11: read command. 10: incremental read command. [25:21] MDIO_PRTAD MDIO Port Address. This is the address of target port (PHY). This is called port address (PRTAD) for Clause 45, and called PHY address (PHYAD) for Clause 22. 0x0 R/W [20:16] MDIO_DEVAD MDIO Device Address. When using Clause 45, this is the device address. When using Clause 22, this is the register address. 0x0 R/W [15:0] MDIO_DATA Data/Address Value. For a write operation (Clause 45 or Clause 22) the SPI host must set this to the 16-bit value to be written. For an address operation (Clause 45), the SPI host must set this to the 16-bit register address value. For a read operation (Clause 45 or Clause 22), or for a read-post-increment-address operation (Clause 45), the SPI host must set this value to 0. On completion of the MDIO transaction (as indicated by TRDONE), the MAC-PHY sets this to the 16-bit value read. 0x0 R/W MAC Tx Frame Size Register Address: 0x30, Reset: 0x00000000, Name: TX_FSIZE Table 57. Bit Descriptions for TX_FSIZE Bits Bit Name Description Reset Access [31:11] RESERVED Reserved. 0x0 R [10:0] TX_FRM_SIZE Transmit Frame Size. This field indicates the size of the frame that is written to the transmit FIFO in bytes when using the generic SPI protocol. The size must include the 2-byte frame header. This is used on the SPI side of the Tx FIFO to determine when the full frame written. When the full frame byte count is reached, subsequent writes to MAC_TX register are ignored until the MAC_TXF_SIZE is written again.This field is only used with the generic SPI protocol. 0x0 R/W MAC Transmit Register Address: 0x31, Reset: 0x00000000, Name: TX The transmit FIFO is written via this register. Table 58. Bit Descriptions for TX Bits Bit Name Description Reset Access [31:0] TDR Transmit Data Register. Writing to this register adds 4 bytes to the host Tx FIFO. Note that the last word of a frame can only contain less than 4 bytes of data. The hardware uses MAC_TXF_SIZE to determine if there is 1 byte, 2 bytes, 3 bytes, or 4 bytes valid in the last SPI write of a frame. Only used with the generic SPI protocol. 0x0 W |
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