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ADIN1110BCPZ-R7 数据表(PDF) 62 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 62 Page - Analog Devices |
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62 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 62 of 107 Table 80. Bit Descriptions for TS_CFG (Continued) Bits Bit Name Description Reset Access written). Note that on writing 1 to this register, the TS_TIMER output immediately toggles from 0 to 1.Writing to this field has no effect if the TS_TIMER has already been enabled. 1 TS_CLR Clear the 1588 Time Stamp Counters. Write a 1 to reset the time stamp counters to 0. This field automatically clears to 0 after it is written to 1. Four counters are cleared, the accumulator, the nanoseconds counter, the seconds counter, and the free running counter. 0x0 W 0 TS_EN Enable the 1588 Time Stamp Counter. When set to 1, the time stamp counter is enabled and time stamps are captured for all received frames. The counters are not cleared when TS_EN is 0, they simply freeze. Therefore, it is recommended to write to use TS_CLR after disabling the counters to get them to a known state before starting again. 0x0 R/W High Period for TS_TIMER Register Address: 0x85, Reset: 0x00000000, Name: TS_TIMER_HI Table 81. Bit Descriptions for TS_TIMER_HI Bits Bit Name Description Reset Access [31:0] TS_TIMER_HI TS_TIMER High Period. This register must be programmed with a value that is divisible by 16 decimal because the counters are driven by a 120 MHz clock and increment in steps of 16. The minimum value that can be written to this field is 16 decimal. 0x0 R/W Low Period for TS_TIMER Register Address: 0x86, Reset: 0x00000000, Name: TS_TIMER_LO Table 82. Bit Descriptions for TS_TIMER_LO Bits Bit Name Description Reset Access [31:0] TS_TIMER_LO TS_TIMER Low Period. This register must be programmed with a value that is divisible by 16 decimal because the counters are driven by a 120 MHz clock and increment in steps of 16.The minimum value that can be written to this field is 16 decimal. 0x0 R/W Quantization Error Correction Register Address: 0x87, Reset: 0x00000000, Name: TS_TIMER_QE_CORR Table 83. Bit Descriptions for TS_TIMER_QE_CORR Bits Bit Name Description Reset Access [31:8] RESERVED Reserved. 0x0 R [7:0] TS_TIMER_QE_CORR TS_TIMER Quantization Error Correction Value. If the required TS_TIMER low and high periods are not directly divisible by 16, program this field with a value between 0 and 15 to compensate for the TS_TIMER quantization error. 0x0 R/W TS_TIMER Counter Start Time Register Address: 0x88, Reset: 0x00000000, Name: TS_TIMER_START Point in Time at Which to Start the TS_TIMER Counter. Table 84. Bit Descriptions for TS_TIMER_START Bits Bit Name Description Reset Access [31:0] TS_TSTART Point in Time at Which to Start the TS_TIMER Counter. Writing to this register starts the TS_TIMER output. To start the TS_TIMER output, this field must be written to a value greater than or equal to 16. After the 0x0 R/W |
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