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ADIN1110BCPZ-R7 数据表(PDF) 93 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 93 Page - Analog Devices |
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93 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 93 of 107 Package Configuration Values Register Device Address: 0x1E; Register Address: 0x8C22, Reset: 0x0000, Name: MGMT_PRT_PKG The MGMT_CFG_VAL address allows reading of the package configuration values. Table 182. Bit Descriptions for MGMT_PRT_PKG Bits Bit Name Description Reset Access [15:6] RESERVED Reserved. 0x0 R [5:0] MGMT_PRT_PKG_VAL Package Type. 0 = 40-lead LFCSP. 0x0 R MDIO Control Register Device Address: 0x1E; Register Address: 0x8C30, Reset: 0x0000, Name: MGMT_MDIO_CNTRL Table 183. Bit Descriptions for MGMT_MDIO_CNTRL Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 MGMT_GRP_MDIO_EN Enable MDIO PHY/Port Group Address Mode. In this mode, the PHY responds to any write or address operation to the 5-bit PHY/Port Address 31 (decimal) regardless of its own PHY/port address. This feature is only intended for initialization sequences in multiport applications, must only be set in those cases, and cleared immediately after the initialization is complete. 0x0 R/W Pin Mux Configuration 1 Register Device Address: 0x1E; Register Address: 0x8C56, Reset: 0x00FE, Name: DIGIO_PINMUX Table 184. Bit Descriptions for DIGIO_PINMUX Bits Bit Name Description Reset Access [15:8] RESERVED Reserved. 0x0 R [7:6] DIGIO_TSTIMER_PINMUX Pin Mux Select for TS_TIMER. 0x3 R/W 00: RXD_1. 01: LED_0. 10: INT. 11: TS_TIMER not assigned. [5:4] DIGIO_TSCAPT_PINMUX Pin Mux Select for TS_CAPT. 0x3 R/W 00: TXD_1. 01: LED_1. 10: MDIO. Others: TS_CAPT not assigned. [3:1] DIGIO_LED1_PINMUX Pin Mux Select for LED_1. 0x7 R/W 000: LED_1. 001: TX_ER. 010: TX_EN. 011: TX_CLK. 100: TXD_0. 101: TXD_2. 110: LINK_ST. 111: LED_1 output not enabled. 0 DIGIO_LINK_ST_POLARITY LINK_ST Polarity. 0x0 R/W |
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