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ADIN1110BCPZ-R7 数据表(PDF) 68 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 68 Page - Analog Devices |
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68 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 68 of 107 The number of frames in the receive FIFO. Table 112. Bit Descriptions for P1_HI_RFC Bits Bit Name Description Reset Access [31:9] RESERVED Reserved. 0x0 R [8:0] P1_HI_RFC Receive Frame Count for the High Priority FIFO. The number of frames in the Rx FIFO. Provided for debug purposes. In store and forward mode, the host software only needs to know that there is at least one frame available. See P1_RX_RDY in the Status Register 1 section. 0x0 R P1 Low Priority Rx FIFO Valid Half Words Register Address: 0xBA, Reset: 0x00000000, Name: P1_LO_RXSIZE Number of valid half words (16 bits) in the low priority Rx FIFO. Table 113. Bit Descriptions for P1_LO_RXSIZE Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. 0x0 R [13:0] P1_LO_RXSIZE Data in the Rx FIFO. Number of half words (16 Bits). 0x0 R P1 High Priority Rx FIFO Valid Half Words Register Address: 0xBB, Reset: 0x00000000, Name: P1_HI_RXSIZE Number of valid half words (16 bits) in the high priority Rx FIFO. Table 114. Bit Descriptions for P1_HI_RXSIZE Bits Bit Name Description Reset Access [31:14] RESERVED Reserved. 0x0 R [13:0] P1_HI_RXSIZE Data in the Rx FIFO. Number of half words (16 bits). 0x0 R PHY CLAUSE 22 REGISTER DETAILS Table 115. PHY Clause 22 Register Summary Address Name Description Reset Access 0x0 MI_CONTROL MII Control Register. 0x1100 R/W 0x1 MI_STATUS MII Status Register. 0x1009 R 0x2 MI_PHY_ID1 PHY Identifier 1 Register. 0x0283 R 0x3 MI_PHY_ID2 PHY Identifier 2 Register. 0xBC91 R 0xD MMD_ACCESS_CNTRL MMD Access Control. 0x0000 R/W 0xE MMD_ACCESS MMD Access. 0x0000 R/W MII Control Register Address: 0x0, Reset: 0x1100, Name: MI_CONTROL This address corresponds to the MII control register specified in Clause 22.2.4.1 of Standard 802.3. Table 116. Bit Descriptions for MI_CONTROL Bits Bit Name Description Reset Access 15 MI_SFT_RST Software Reset. The software reset register allows a software reset cycle to be initiated. Mirrors CRSM_SFT_RST. 0x0 R/W SC 14 MI_LOOPBACK Local Loopback (PCS). The loopback register allows the PHY loopback mode to be engaged. Mirrors LB_PCS_EN. 0x0 R/W |
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