ADIN1110BCPZ-R7 datasheet(43/107 Pages) AD

43 / 107 page

Data Sheet

ADIN1110

MAC SPI

analog.com

Rev. B | 43 of 107

To forward frames with this DA to the host, set the TO_HOST

bit within the ADDR_FILT_UPRn to 1. To apply this rule, set the

APPLY2PORT1 bit to 1.

MAC addresses can be masked using the ADDR_MSK_x registers.

For example, to receive all the MAC addresses in the range 0x8000

005A 64xx, write:

1. 0xFFFF to ADDR_MSK_UPR0.

2. 0XFFFFFF00 to ADDR_MSK_LWR0.

Frames that do not match any of the 16 ADDR_FILT_x registers

are dropped by default. If the P1_FWD_UNK2HOST bits within the

CONFIG2 register are set to 1, all frames that do not match a DA

are forwarded to the host. Figure 30 shows the filtering algorithm.

Figure 30. Filtering Algorithm

Frames received with a bad CRC or with RX_ER asserted from the

PHY, as well as runt and jabber frames, are dropped and counted.

Receive Priority Queues

There are two different FIFOs on receive: a high priority FIFO and a

low priority FIFO.

By default, the low priority FIFO is configured to 12 kB, and the

high priority FIFO is configured to 8 kB. The sizes of these FIFOs

can be changed before receiving or transmitting any frames via

the P1_RX_LO_SIZE and P1_RX_HI_SIZE fields in the FIFO_SIZE

Frames are always returned from the high priority FIFO first.

Statistics Counters

There are 15 32-bit counters on the receive port that increment on

each frame transmit and receive.

Table 37. Statistics Counters

Name

Description

P1_RX_FRM_CNT

Rx frame count

P1_RX_UCAST_CNT

Rx unicast frame count

P1_RX_MCAST_CNT

Rx multicast frame count

P1_RX_BCAST_CNT

Rx broadcast frame count

P1_RX_CRC_ERR_CNT

Rx CRC errored frame count

P1_RX_ALGN_ERR_CNT

Rx alignment error count

P1_RX_PHY_ERR_CNT

Rx PHY error count

P1_RX_LS_ERR_CNT

Rx long and short frame error count

P1_TX_FRM_CNT

Tx frame count

P1_TX_UCAST_CNT

Tx unicast frame count

P1_TX_MCAST_CNT

Tx multicast frame count

P1_TX_BCAST_CNT

Tx broadcast frame count

P1_RX_DROP_FULL_CNT

Rx frames dropped due to FIFO full

P1_RX_DROP_FILT_CNT

Rx frames dropped due to filtering

P1_RX_IFG_ERR_CNT

Rx frames received with interframe gap (IFG)

errors

Receive Drop FIFO Full Counter

Before the first byte of a received frame is written into the appropri-

ate receive FIFO, the space in the FIFO is checked. If there is

no space for at least 256 bytes, the frame is dropped and the

P1_RX_DROP_FULL_CNT counter increments. If there is space

for at least 256 bytes in the FIFO, the logic commences writing

the frame to the receive FIFO. If the received frame exceeds 256

bytes and the receive FIFO fills, the frame is dropped and the

P1_RX_DROP_FULL_CNT counter increments.

Frame Receive and Transmit Errors

By default, all received errored frames are dropped and counted.

Received errored frames do not generate interrupts. Instead, they

are dropped and counted, and the software must monitor the

statistics counters.

SRAM ECC Error

When writing a frame to the FIFO, the size of the frame is inserted

in a 16-bit word at the front of the frame and written to the FIFO. A

5-bit error correction code (ECC) is placed alongside the size field.

When this location is read from static random-access memory

(SRAM), the ECC is checked. If a double bit error is detected,

the RX_ECC_ERR or TX_ECC_ERR bits of the STATUS1 register

assert. If a double bit error is detected on reading a frame header

from the receive FIFO, the frame is not transmitted.

In response to an ECC error, a FIFO automatically clears. All

frames in the FIFO are lost, transmission stops, and a bad CRC

ADIN1110BCPZ-R7 数据表(PDF) 43 Page - Analog Devices

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