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ADIN1110BCPZ-R7 数据表(PDF) 77 Page - Analog Devices |
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ADIN1110BCPZ-R7 数据表(HTML) 77 Page - Analog Devices |
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77 / 107 page  Data Sheet ADIN1110 REGISTERS analog.com Rev. B | 77 of 107 PMA/PMD Transmit Disable Register Device Address: 0x01; Register Address: 0x0009, Reset: 0x0000, Name: PMA_PMD_TX_DIS This address corresponds to the PMD transmit disable register specified in Clause 45.2.1.8 of Standard 802.3. Table 129. Bit Descriptions for PMA_PMD_TX_DIS Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 PMA_TX_DIS PMD Transmit Disable. When this bit is set to 1, the PMD disables output on the transmit path. Otherwise, the PMD enables output on the transmit path. 0x0 R/W PMA/PMD Extended Abilities Register Device Address: 0x01; Register Address: 0x000B, Reset: 0x0800, Name: PMA_PMD_EXT_ABILITY PMA/PMD extended abilities. Table 130. Bit Descriptions for PMA_PMD_EXT_ABILITY Bits Bit Name Description Reset Access [15:12] RESERVED Reserved. 0x0 R 11 PMA_PMD_BT1_ABLE PHY Supports BASE-T1. Indicates that the PHY supports BASE-T1 extended abilities as listed in PMA_PMD_BT1_ABILITY. 0x1 R [10:0] RESERVED Reserved. 0x0 R BASE-T1 PMA/PMD Extended Ability Register Device Address: 0x01; Register Address: 0x0012, Reset: 0x0004, Name: PMA_PMD_BT1_ABILITY This address corresponds to the BASE-T1 PMA/PMD extended ability register specified in Clause 45.2.1.16 of Standard 802.3. This register is read only, and writes have no effect. Table 131. Bit Descriptions for PMA_PMD_BT1_ABILITY Bits Bit Name Description Reset Access [15:4] RESERVED Reserved. 0x0 R 3 B10S_ABILITY 10BASE-T1S Ability. This bit always reads as 0 because the PMA/PMD does not support 10BASE-T1S. 0x0 R 2 B10L_ABILITY 10BASE-T1L Ability. This bit always reads as 1 because the PMA/PMD supports 10BASE-T1L. 0x1 R 1 B1000_ABILITY 1000BASE-T1 Ability. This bit always reads as 0 because the PMA/PMD does not support 1000BASE- T1. 0x0 R 0 B100_ABILITY 100BASE-T1 Ability. This bit always reads as 0 because the PMA/PMD does not support 100BASE-T1. 0x0 R BASE-T1 PMA/PMD Control Register Device Address: 0x01; Register Address: 0x0834, Reset: 0x8002, Name: PMA_PMD_BT1_CONTROL This address corresponds to the BASE-T1 PMA/PMD control register specified in Clause 45.2.1.185 of Standard 802.3. Table 132. Bit Descriptions for PMA_PMD_BT1_CONTROL Bits Bit Name Description Reset Access 15 RESERVED Reserved. 0x1 R 14 CFG_MST Master and Slave Configuration. CFG_MST is used only when autonegotiation is disabled. Otherwise, this value is determined by the autonegotiation process itself. When this bit is set as 1, the device is configured as master. Otherwise, the device is configured as slave. Pin Dependent R/W [13:4] RESERVED Reserved. 0x0 R |
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