ADIN1110BCPZ-R7 datasheet(18/107 Pages) AD

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Data Sheet

ADIN1110

HARDWARE CONFIGURATION PINS

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Rev. B | 18 of 107

ADIN1110 and it is strongly recommended that autonegotiation is

always enabled.

During autonegotiation, when prefer slave is selected and the

remote end is prefer or forced master, the local PHY is set to slave

(and remote to master). When the remote end is prefer or forced

slave, the local PHY is set to master (and remote to slave).

Table 14. Master/Slave Selection (Hardware Configuration)

Master/Slave Selection

MS_SEL

Prefer Slave Selection

Prefer Master Selection

Transmit Amplitude

The TX2P4_EN hardware configuration pin allows the user to

configure the required transmit amplitude mode for the intended ap-

plication (see Table 15). If TX2P4_EN is pulled low, the ADIN1110

is configured by default to support both 1.0 V p-p and 2.4 V p-p

transmit levels, decided by autonegotiation. If TX2P4_EN is pulled

high, the ADIN1110 is configured to disable 2.4 V p-p transmit

operating mode by default and operate with 1.0 V p-p transmit

level only. If the TX2P4_EN pin is strapped high (1.0 V p-p only),

the associated register cannot be changed through the SPI. For

example, 2.4 V p-p operation is not possible if the ADIN1110 is

hardware pin configured for 1.0 V p-p only.

The 1.0 V p-p transmit operating mode supports the spur use case

and can operate at a lower AVDD_H supply voltage of 1.8 V. This

supports intrinsic safe applications.

The higher transmit operating mode of 2.4 V p-p supports trunk

applications and requires a higher AVDD_H supply voltage of 3.3

V. This mode can be used for longer cable lengths in industrial

Ethernet environments with high noise levels.

Table 15. Transmit Amplitude Configuration (Hardware Configuration)

Transmit Amplitude Selection

TX2P4_EN

1.0 V p-p or 2.4 V p-p

1.0 V p-p

SPI Protocol Configuration

The ADIN1110 allows the use of a generic SPI protocol with or

without the use of CRC, or the OPEN Alliance SPI protocol with or

without protection.

Table 16. SPI Protocol (Hardware Configuration)

SPI Protocol

SPI_CFG1

SPI_CFG0

OPEN Alliance with Protection

OPEN Alliance Without Protection

Generic SPI with 8-bit CRC

Generic SPI Without 8-bit CRC

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