ADIN1110BCPZ-R7 datasheet(42/107 Pages) AD

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Data Sheet

ADIN1110

MAC SPI

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Rev. B | 42 of 107

immediately attempts to bring up links as configured by the other

hardware configuration pins. In managed applications, software is

available to configure the PHY via the management interface. In

this case, it is possible to use the hardware configuration pins to

configure the PHY to enter software power-down mode after reset,

such that the PHY can be configured before linking is attempted.

Recommended Register Operation

Many of the PHY registers in the ADIN1110 are defined in the IEEE

Standard 802.3, and the exact behavior of these registers follows

the standard. This behavior may not always be obvious and is

described in this section, including the recommended operation and

use of the registers.

Latch Low Registers

The IEEE Standard 802.3-2018 requires certain MDIO accessi-

ble registers to exhibit latch low behavior. The idea is to allow

software that only intermittently reads these registers to detect

conditions that can be transitory or short lived. For example, the

AN_LINK_STATUS bit is required to latch low. When the device

exits from a reset or power-down state, the latching condition is

not active and the value of the AN_LINK_STATUS bit reflects the

current status of the link. However, if the link comes up and drops,

the latching condition is active. In this case, the AN_LINK_STATUS

bit reads as 0 even if the link has come back up again in the inter-

im. The latching condition is only cleared when the AN_LINK_STA-

TUS bit is read, ensuring the software has had the opportunity to

observe that the link dropped.

One implication of this latch low behavior is that, if software wishes

to determine the current status of the link, it must perform two reads

of the AN_LINK_STATUS bit back to back. The first read is needed

to clear any active latching condition.

Another implication is that it is important that software take ac-

count of the interaction between MDIO accessible bits that share

a register address. For example, the AN_PAGE_RX bits and

AN_LINK_STATUS bits reside at the same register address. As

a result, reading the AN_PAGE_RX bits clears any active latching

condition associated with the AN_LINK_STATUS bits.

IEEE Duplicated Registers

The IEEE Standard 802.3-2018 covers a very wide range of

standards and speeds, from 10 Mbps to 40 Gbps and higher,

and includes a very large number of clauses. There are registers

associated with many clauses, and different PHYs can include

different clauses and combinations of clauses. Therefore, registers

for common functions like software reset, software power-down,

loopback, and so on, tend to be implemented in multiple clauses.

In the ADIN1110, the physical implementation of these registers is

in a single location, but they can be accessed at multiple address-

es. For example, the software reset bit, can be read or written in

all the following IEEE MMD locations and vendor specific register

locations:

►

PMA_SFT_RST

►

B10L_PMA_SFT_RST

►

PCS_SFT_RST

►

B10L_PCS_SFT_RST

►

CRSM_SFT_RST

In this example, these are the PMA/PMD, PCS, autonegotiation,

and Vendor Specific MMD 1 device address locations (per Table

36).

Having multiple address locations for the same register makes

the use of the device more complex than necessary, particularly

in relation to registers that have latch low or self clear access

permissions. This is an unavoidable consequence of the IEEE

standard.

The ADIN1110 data sheet only calls out a single recommended

address location for each of these IEEE registers to simplify the

operation and use of the device. In general, the registers intro-

duced in the 802.3cg (10BASE-T1L) section of the standard are

recommended over older (equivalent) registers. Often, registers in

a vendor specific address are recommended, particularly where a

all the IEEE register address locations covered by the 10BASE-T1L

standard when the start-up is complete after a power-on reset,

hardware reset, or software reset.

Read Modify Write Operation

All register write operations must be performed as read modify write

operations. If this process is not followed, the value of the register

bits can inadvertently change.

MAC

Frame Filtering on Receive

By default, the device filters all frames received. To receive frames,

set up the address filtering table, or the default operation for all

received frames can be changed.

The device can be configured to filter up to 16 different MAC

addresses based on the destination MAC address (DA).

To receive frames with a particular DA, that DA has to be program-

med to one of the 16 ADDR_FILT_x registers. Each register is 32

bits wide. Therefore, for example, to program a DA of 0800 005A

646B to ADDR_FILT[0], write the following:

1. 0x0800 to ADDR_FILT_UPR0.

2. 0x005A6468 to ADDR_FILT_LWR0.

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