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ST7LITE49M 数据表(PDF) 108 Page - STMicroelectronics |
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ST7LITE49M 数据表(HTML) 108 Page - STMicroelectronics |
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108 / 188 page ![]() On-chip peripherals ST7LITE49M 108/188 Bit 0 = TB2F Timebase 2 Interrupt flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred Lite Timer Autoreload register (LTARR) Reset value: 0000 0000 (00h) Bits 7:0 = AR[7:0] Counter 2 Reload value These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. Lite Timer Counter 2 (LTCNTR) Reset value: 0000 0000 (00h) Bits 7:0 = CNT[7:0] Counter 2 Reload value This register is read by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. Lite Timer Control/status register (LTCSR1) Reset value: 0x00 0000 (x0h) Bit 7 = ICIE Interrupt Enable bit This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled 7 0 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 Read / Write 7 0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Read only 7 0 ICIE ICF TB TB1IE TB1F Read / Write |
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