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ST7LITE49M 数据表(PDF) 131 Page - STMicroelectronics |
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ST7LITE49M 数据表(HTML) 131 Page - STMicroelectronics |
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131 / 188 page  ST7LITE49M On-chip peripherals 131/188 11.5.6 Register description Control/status register (ADCCSR) Reset value: 0000 0000 (00h) Bit 7 = EOC End of Conversion bit This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register or writes to any bit of the ADCCSR register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED ADC clock selection bit This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit description (ADCDRL register). Bit 5 = ADON A/D Converter on bit This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bits 4:3 = Reserved. Must be kept cleared. Bits 2:0 = CH[2:0] Channel Selection These bits select the analog input to convert. They are set and cleared by software. 7 0 EOC SPEED ADON 0 CH3 CH2 CH1 CH0 Read only Read/write Table 54. Channel selection using CH[2:0] Channel Pin(1) 1. The number of channels is device dependent. Refer to the device pinout description. CH3 CH2 CH1 CH0 AIN0 0 0 0 0 AIN1 0 0 0 1 AIN2 0 0 1 0 AIN3 0 0 1 1 AIN4 0 1 0 0 AIN5 0 1 0 1 AIN6 0 1 1 0 AIN7 0 1 1 1 AIN8 1 0 0 0 AIN9 1 0 0 1 |
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