ST7LITE49M datasheet(154/188 Pages) STMICROELECTRONICS

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Electrical characteristics

ST7LITE49M

154/188

13.6

Clock and timing characteristics

Subject to general operating conditions for VDD, fOSC, and TA.

Figure 72.

Typical application with an external clock source

Table 78.

General timings

Symbol

Parameter(1)

Guaranteed by Design. Not tested in production.

Conditions

Min

Typ(2)

Data based on typical application software.

Max

Unit

tc(INST)

Instruction cycle time

fCPU=8MHz

tCPU

250

375

1500

tv(IT)

Interrupt reaction time(3)

tv(IT) = ∆tc(INST) + 10

Time measured between interrupt event and interrupt vector fetch.

∆t

c(INST) is the number of tCPU cycles

needed to finish the current instruction execution.

fCPU=8MHz

tCPU

1.25

2.75

µs

Table 79.

External clock source characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VOSC1H or

VCLKIN_H

OSC1/CLKIN input pin high

level voltage

see Figure 72

0.7xVDD

VDD

VOSC1L or

VCLKIN_L

OSC1/CLKIN input pin low

level voltage

VSS

0.3xVDD

tw(OSC1H) or

tw(CLKINH)

tw(OSC1L) or

tw(CLKINL)

OSC1/CLKIN high or low

time(1)

Data based on design simulation and/or technology characteristics, not tested in production.

tr(OSC1) or tr(CLKIN)

tf(OSC1) or tf(CLKIN)

OSC1/CLKIN rise or fall time(1)

OSCx/CLKIN Input leakage

current

VSS≤VIN≤VDD

±1

µA

OSC1/CLKIN

OSC2

fOSC

EXTERNAL

ST7xxx

CLOCK SOURCE

Not connected internally

VOSC1L or VCLKINL

VOSC1H or VCLKINH

tr(OSC1 or CLKIN))

tf(OSC1 or CLKIN)

tw(OSC1H or CLKINH))

tw(OSC1L or CLKINL)

90%

10%

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