ST7LITE49M datasheet(175/188 Pages) STMICROELECTRONICS

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ST7LITE49M

Device configuration and ordering information

175/188

Device configuration and ordering information

This device is available for production in user programmable version (Flash).

ST7LITE49M XFlash devices are shipped to customers with a default program memory

content (FFh).

14.1

Option bytes

The two option bytes allow the hardware configuration of the microcontroller to be selected.

The option bytes can be accessed only in programming mode (for example using a standard

ST7 programming tool).

14.1.1

Option byte 1

●

Bit 7:6 = CKSEL[1:0] Start-up clock selection. These bits are used to select the startup

frequency. By default, the internal RC is selected.

●

Bits 5:4 = Reserved, must always be 1.

●

Bits 3:2 = LVD[1:0] Low Voltage Detection selection. These option bits enable the low

voltage detection block (LVD) with a selected threshold as shown in Table 97.

●

Bit 1 = WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

●

Bit 0 = WDG HALT Watchdog Reset on Halt

This option bit determines if a Reset is generated when entering Halt mode while the

Watchdog is active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

Table 96.

Startup clock selection

Configuration

CKSEL1

CKSEL0

Internal RC as Startup Clock

AWU RC as a Startup Clock

External crystal/ceramic resonator

External Clock

Table 97.

LVD threshold configuration

Configuration

VD1

VD0

LVD Off (default value)

Highest Voltage Threshold

Medium Voltage Threshold

Lowest Voltage Threshold

ST7LITE49M 数据表(PDF) 175 Page - STMicroelectronics

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