ST7LITE49M datasheet(172/188 Pages) STMICROELECTRONICS

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Electrical characteristics

ST7LITE49M

172/188

Figure 97.

RESET pin protection when LVD is disabled

The reset network protects the device against parasitic resets.

The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.

Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin

can go below the VIL max. level specified in Section 13.10.1 on page 170. Otherwise the reset will not be

taken into account internally.

Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user

must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for

IINJ(RESET) in Section Table 66. on page 144.

Please refer to Section 12.2.1 on page 139 for more details on illegal opcode reset conditions.

13.11

10-bit ADC characteristics

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

0.01

µF

EXTERNAL

RESET

CIRCUIT

USER

Required

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

INTERNAL

RESET

WATCHDOG

ILLEGAL OPCODE 5)

Table 92.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ(1)

Max

Unit

fADC

ADC clock frequency(2)

4MHz

VAIN

Conversion voltage range

VSSA

VDDA

RAIN

External input resistor

VDD = 5V, fADC=4MHz

8k(3)

Ω

VDD = 3.3V, fADC=4MHz

7k(3)

2.7V

≤ V

DD ≤ 5.5V, fADC=2MHz

10k(3)

2.4V

≤ V

DD ≤ 2.7V, fADC=1MHz

20k(3)

CADC

Internal sample and hold capacitor

tSTAB

Stabilization time after ADC enable

CPU=8MHz, fADC=4MHz

0(4)

µs

tADC

Conversion time (Sample+Hold)

3.5

- Sample capacitor loading time

- Hold conversion time

1/fADC

Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guidelines

and are not tested.

The maximum ADC clock frequency allowed within VDD = 2.4V to 2.7V operating range is 1MHz.

Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum

value). Data guaranteed by Design, not tested in production.

The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then always

valid.

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