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TMP93CS41 数据表(PDF) 136 Page - Toshiba Semiconductor

部件名 TMP93CS41
功能描述  CMOS 16-Bit Microcontroller
PDF  248 Pages
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制造商  TOSHIBA [Toshiba Semiconductor]
网页  http://www.semicon.toshiba.co.jp/eng
标志 TOSHIBA - Toshiba Semiconductor

TMP93CS41 数据表(HTML) 136 Page - Toshiba Semiconductor

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TMP93CS40/TMP93CS41
2004-02-10
93CS40-134
7
6
5
4
3
2
1
0
Bit symbol
CAP2T5
EQ5T5
CAP1IN
CAP12M1
CAP12M0
CLE
T4CLK1
T4CLK0
Read/Write
R/W
W
R/W
R/W
R/W
After reset
0
0
1
0
0
0
0
0
TFF5 invert trigger
0: Disable trigger
1: Enable trigger
Function
Inverted
when the
UC value is
latched to
CAP2
Inverted
when the
up counter
matches
TREG5
0: Software
capture
1: Don’t
care
Capture timing
00: Disable
INT4 occurs at rising
edge.
01: TI4 ↑
TI5 ↑
INT4 occurs at rising
edge.
10: TI4 ↑
TI4 ↓
INT4 occurs at falling
edge.
11: TFF1 ↑
TFF1 ↓
INT4 occurs at rising
edge.
1: UC4
clear
enable
Timer 4 source clock
00: TI4
01: φT1
10: φT4
11: φT16
Figure 3.9.4 16-Bit Timer Controller Register (T4MOD) (2/2)
Capture control
INT4 control
00
Capture disable
01
CAP1 at TI4 rise
CAP2 at TI5 rise
Interrupt occurs at the rising
edge of TI4 (INT4) input.
10
CAP1 at TI4 rise
CAP2 at TI4 fall
Interrupt occurs at the falling
edge of TI4 (INT4) input.
11
CAP1 at TFF1 rise
CAP2 at TFF1 fall
Interrupt occurs at the rising
edge of TI4 (INT4) input.
Capture timing of timer4
0
The up counter 4 value is loaded to CAP1
(Software capture)
1
Always read as “1”
Software capture
0
Trigger disable (Invert prohibition)
1
Trigger enable (Invert permission)
Timer flip-flop 5 (TFF5) invert trigger
CAP2T5: Inverted when the up counter value is latched to CAP2
EQ5T5: Inverted when the up counter matches TREG5
T4MOD
(0038H)



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