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TMP93CS41 数据表(PDF) 137 Page - Toshiba Semiconductor |
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TMP93CS41 数据表(HTML) 137 Page - Toshiba Semiconductor |
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137 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-135 7 6 5 4 3 2 1 0 Bit symbol TFF5C1 TFF5C0 CAP2T4 CAP1T4 EQ5T4 EQ4T4 TFF4C1 TFF4C0 Read/Write W R/W R/W R/W R/W W After reset 1 1 0 0 0 0 1 1 TFF4 invert trigger 0: Disable trigger 1: Enable trigger Function 00: Invert TFF5 01: Set TFF5 10: Clear TFF5 11: Don’t care * Always read as “11” Inverted when the UC value is latched to CAP2 Inverted when the UC value is latched to CAP1 Inverted when the UC value matches TREG5 Inverted when the UC value matches TREG4 00: Invert TFF4 01: Set TFF4 10: Clear TFF4 11: Don’t care * Always read as “11” Figure 3.9.5 16-Bit Timer 4 F/F Control (T4FFCR) 00 Inverts the TFF4 value (Software inversion) 01 Sets TFF4 to “1” 10 Clear TFF4 to “0” 11 Don’t care (Always read as “11”) Timer flip-flop 4 (TFF4) control 0 Trigger disable (Invert prohibition) 1 Trigger enable (Invert permission) Timer flip-flop 4 (TFF4) invert trigger CAP2T4: Inverted when the up counter value is latched to CAP2 CAP1T4: Inverted when the up counter value is latched to CAP1 EQ5T4: Inverted when up counter matches TREG5 EQ4T4: Inverted when up counter matches TREG4 00 Inverts the TFF5 value (Software inversion) 01 Set TFF5 to “1” 10 Clear TFF5 to “0” 11 Don’t care (Always read as “11”) Timer flip-flop 5 (TFF5) control T4FFCR (0039H) |
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