ST10F271 datasheet(164/173 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F271

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Figure 58.

CLKOUT and READY

Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled

LOW at this sampling point terminates the currently running bus cycle.

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or

WR).

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to

CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is

guaranteed, if READY is removed in response to the command (see Note 4).

Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state

may be inserted here.

For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus

without MTTC wait state this delay is zero.

The next external bus cycle may start here.

24.8.19

External bus arbitration

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

t30

t34

t35

t36

t35

t36

t58

t59

t58

t59

wait state

READY

MUX / Tri-state 6)

t32

t33

t29

Running cycle 1)

t31

t37

t60 4)

CLKOUT

ALE

RD, WR

Synchronous

Asynchronous

READY

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