ST10F271 datasheet(167/173 Pages) STMICROELECTRONICS

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ST10F271

Electrical characteristics

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Figure 61.

SSC master timing

The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock

edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading

clock edge is low-to-high transition (SSCPO = 0b).

The bit timing is repeated for all bits to be transmitted or received.

Slave mode

VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

t308p

Read data hold time after latch

edge, phase error detection on

(SSCPEN = 1)

–

4TCL

–

t307

Read data setup time before latch

edge, phase error detection off

(SSCPEN = 0)

–

2TCL

–

t308

Read data hold time after latch

edge, phase error detection off

(SSCPEN = 0)

0–0

–

Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with

48MHz CPU clock and <SSCBR> set to ‘2h’. When 40MHz CPU clock is used the maximum baudrate cannot be higher

than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only

with CPU clock equal to (or lower than) 32MHz.

Formula for SSC Clock Cycle time: t300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC

Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125ns (corresponding to 8Mbaud).

Partially tested, guaranteed by design characterization.

Table 81.

SSC master mode timings

Symbol

Parameter

Max. Baudrate 6.6MBd

(1)@F

CPU = 40MHz

(<SSCBR> = 0002h)

Variable Baudrate

(<SSCBR> = 0001h -

FFFFh)

Unit

min.

max.

min.

max.

1st out bit

Last out bit

2nd out bit

2nd In bit

1st in bit

Last in bit

SCLK

MTSR

MRST

t308

t307

t308

t307

t305

t300

t301

t302

t304

t303

t306

t305

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