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ST10F271 数据表(PDF) 169 Page - STMicroelectronics |
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ST10F271 数据表(HTML) 169 Page - STMicroelectronics |
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169 / 173 page  ST10F271 Electrical characteristics 169/173 Figure 62. SSC slave timing 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. 1st out bit Last out bit 2nd out bit 1) 2) 2nd in bit 1st in bit Last in bit SCLK MRST MTSR t313 t314 t315 t316 t315 t317 t318 t317 t318 t315 t310 t311 t312 |
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